begriffs open source - cmsis/blob - v6.0.0/Core_A/group__CMSIS__ACTLR.html

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 127   <div class="summary">
 128 <a href="#groups">Content</a> &#124;
 129 <a href="#nested-classes">Data Structures</a> &#124;
 130 <a href="#func-members">Functions</a>  </div>
 131   <div class="headertitle"><div class="title">Auxiliary Control Register (ACTLR)<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a></div></div></div>
 132 </div><!--header-->
 133 <div class="contents">
 134
 135 <p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 136 <a href="#details">More...</a></p>
 137 <table class="memberdecls">
 138 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
 139 Content</h2></td></tr>
 140 <tr class="memitem:group__CMSIS__ACTLR__BITS"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html">ACTLR Bits</a></td></tr>
 141 <tr class="memdesc:group__CMSIS__ACTLR__BITS"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit position and mask macros. <br /></td></tr>
 142 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 143 </table><table class="memberdecls">
 144 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
 145 Data Structures</h2></td></tr>
 146 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html">ACTLR_Type</a></td></tr>
 147 <tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit field declaration for ACTLR layout.  <a href="unionACTLR__Type.html#details">More...</a><br /></td></tr>
 148 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 149 </table><table class="memberdecls">
 150 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
 151 Functions</h2></td></tr>
 152 <tr class="memitem:ga6317030a08c8c015425ffd0e3e7dae17"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armclang__a_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#ga6317030a08c8c015425ffd0e3e7dae17">__set_ACTLR</a> (uint32_t actlr)</td></tr>
 153 <tr class="memdesc:ga6317030a08c8c015425ffd0e3e7dae17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set ACTLR.  <br /></td></tr>
 154 <tr class="separator:ga6317030a08c8c015425ffd0e3e7dae17"><td class="memSeparator" colspan="2">&#160;</td></tr>
 155 <tr class="memitem:gae75d412bfd6fe873ade00b021aefcab3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armclang__a_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> (void)</td></tr>
 156 <tr class="memdesc:gae75d412bfd6fe873ade00b021aefcab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get ACTLR.  <br /></td></tr>
 157 <tr class="separator:gae75d412bfd6fe873ade00b021aefcab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 158 </table>
 159 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 160 <p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. </p>
 161 <p>The ACTLR characteristics are differs between various Armv7-A implementations.</p>
 162 <p><b>Cortex-A5</b></p>
 163 <table class="markdownTable">
 164 <tr class="markdownTableHead">
 165 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 166 <tr class="markdownTableRowOdd">
 167 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 168 <tr class="markdownTableRowEven">
 169 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DBDI   </td><td class="markdownTableBodyLeft">Disable Branch Dual Issue    </td></tr>
 170 <tr class="markdownTableRowOdd">
 171 <td class="markdownTableBodyLeft">[27:19]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 172 <tr class="markdownTableRowEven">
 173 <td class="markdownTableBodyLeft">[18]   </td><td class="markdownTableBodyLeft">BTDIS   </td><td class="markdownTableBodyLeft">Disable indirect Branch Target Address Cache (BTAC).    </td></tr>
 174 <tr class="markdownTableRowOdd">
 175 <td class="markdownTableBodyLeft">[17]   </td><td class="markdownTableBodyLeft">RSDIS   </td><td class="markdownTableBodyLeft">Disable return stack operation.    </td></tr>
 176 <tr class="markdownTableRowEven">
 177 <td class="markdownTableBodyLeft">[16:15]   </td><td class="markdownTableBodyLeft">BP   </td><td class="markdownTableBodyLeft">Branch prediction policy.    </td></tr>
 178 <tr class="markdownTableRowOdd">
 179 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 180 <tr class="markdownTableRowEven">
 181 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">RADIS   </td><td class="markdownTableBodyLeft">Disable Data Cache read-allocate mode.    </td></tr>
 182 <tr class="markdownTableRowOdd">
 183 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">DWBST   </td><td class="markdownTableBodyLeft">Disable AXI data write bursts to Normal memory.    </td></tr>
 184 <tr class="markdownTableRowEven">
 185 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 186 <tr class="markdownTableRowOdd">
 187 <td class="markdownTableBodyLeft">[9:8]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 188 <tr class="markdownTableRowEven">
 189 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 190 <tr class="markdownTableRowOdd">
 191 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 192 <tr class="markdownTableRowEven">
 193 <td class="markdownTableBodyLeft">[5:1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 194 <tr class="markdownTableRowOdd">
 195 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 196 </table>
 197 <p><b>Cortex-A7</b></p>
 198 <table class="markdownTable">
 199 <tr class="markdownTableHead">
 200 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 201 <tr class="markdownTableRowOdd">
 202 <td class="markdownTableBodyLeft">[31:29]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 203 <tr class="markdownTableRowEven">
 204 <td class="markdownTableBodyLeft">[28]   </td><td class="markdownTableBodyLeft">DDI   </td><td class="markdownTableBodyLeft">Disable Dual Issue    </td></tr>
 205 <tr class="markdownTableRowOdd">
 206 <td class="markdownTableBodyLeft">[27:16]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 207 <tr class="markdownTableRowEven">
 208 <td class="markdownTableBodyLeft">[15]   </td><td class="markdownTableBodyLeft">DDVM   </td><td class="markdownTableBodyLeft">Disable Distributed Virtual Memory transactions.    </td></tr>
 209 <tr class="markdownTableRowOdd">
 210 <td class="markdownTableBodyLeft">[14:13]   </td><td class="markdownTableBodyLeft">L1PCTL   </td><td class="markdownTableBodyLeft">L1 Data prefetch control.    </td></tr>
 211 <tr class="markdownTableRowEven">
 212 <td class="markdownTableBodyLeft">[12]   </td><td class="markdownTableBodyLeft">L1RADIS   </td><td class="markdownTableBodyLeft">L1 Data Cache read-allocate mode disable.    </td></tr>
 213 <tr class="markdownTableRowOdd">
 214 <td class="markdownTableBodyLeft">[11]   </td><td class="markdownTableBodyLeft">L2RADIS   </td><td class="markdownTableBodyLeft">L2 Data Cache read-allocate mode disable.    </td></tr>
 215 <tr class="markdownTableRowEven">
 216 <td class="markdownTableBodyLeft">[10]   </td><td class="markdownTableBodyLeft">DODMBS   </td><td class="markdownTableBodyLeft">Disable optimized data memory barrier behavior.    </td></tr>
 217 <tr class="markdownTableRowOdd">
 218 <td class="markdownTableBodyLeft">[9:7]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 219 <tr class="markdownTableRowEven">
 220 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 221 <tr class="markdownTableRowOdd">
 222 <td class="markdownTableBodyLeft">[5:0]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.   </td></tr>
 223 </table>
 224 <p><b>Cortex-A9</b></p>
 225 <table class="markdownTable">
 226 <tr class="markdownTableHead">
 227 <th class="markdownTableHeadLeft">Bits   </th><th class="markdownTableHeadLeft">Name   </th><th class="markdownTableHeadLeft">Function    </th></tr>
 228 <tr class="markdownTableRowOdd">
 229 <td class="markdownTableBodyLeft">[31:10]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 230 <tr class="markdownTableRowEven">
 231 <td class="markdownTableBodyLeft">[9]   </td><td class="markdownTableBodyLeft">PARITY   </td><td class="markdownTableBodyLeft">Support for parity checking, if implemented.    </td></tr>
 232 <tr class="markdownTableRowOdd">
 233 <td class="markdownTableBodyLeft">[8]   </td><td class="markdownTableBodyLeft">AOW   </td><td class="markdownTableBodyLeft">Enable allocation in one cache way only.    </td></tr>
 234 <tr class="markdownTableRowEven">
 235 <td class="markdownTableBodyLeft">[7]   </td><td class="markdownTableBodyLeft">EXCL   </td><td class="markdownTableBodyLeft">Exclusive L1/L2 cache control.    </td></tr>
 236 <tr class="markdownTableRowOdd">
 237 <td class="markdownTableBodyLeft">[6]   </td><td class="markdownTableBodyLeft">SMP   </td><td class="markdownTableBodyLeft">Enables coherent requests to the processor.    </td></tr>
 238 <tr class="markdownTableRowEven">
 239 <td class="markdownTableBodyLeft">[5:4]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 240 <tr class="markdownTableRowOdd">
 241 <td class="markdownTableBodyLeft">[3]   </td><td class="markdownTableBodyLeft">WFLZM   </td><td class="markdownTableBodyLeft">Enable write full line of zeros modea.    </td></tr>
 242 <tr class="markdownTableRowEven">
 243 <td class="markdownTableBodyLeft">[2]   </td><td class="markdownTableBodyLeft">L1PE   </td><td class="markdownTableBodyLeft">Dside prefetch.    </td></tr>
 244 <tr class="markdownTableRowOdd">
 245 <td class="markdownTableBodyLeft">[1]   </td><td class="markdownTableBodyLeft">-   </td><td class="markdownTableBodyLeft">Reserved.    </td></tr>
 246 <tr class="markdownTableRowEven">
 247 <td class="markdownTableBodyLeft">[0]   </td><td class="markdownTableBodyLeft">FW   </td><td class="markdownTableBodyLeft">Cache and TLB maintenance broadcast.   </td></tr>
 248 </table>
 249 <p>Consider using <a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> and <a class="el" href="group__CMSIS__ACTLR.html#ga6317030a08c8c015425ffd0e3e7dae17">__set_ACTLR</a> to access ACTRL register. </p>
 250 <h2 class="groupheader">Function Documentation</h2>
 251 <a id="gae75d412bfd6fe873ade00b021aefcab3" name="gae75d412bfd6fe873ade00b021aefcab3"></a>
 252 <h2 class="memtitle"><span class="permalink"><a href="#gae75d412bfd6fe873ade00b021aefcab3">&#9670;&#160;</a></span>__get_ACTLR()</h2>
 253
 254 <div class="memitem">
 255 <div class="memproto">
 256       <table class="memname">
 257         <tr>
 258           <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_ACTLR </td>
 259           <td>(</td>
 260           <td class="paramtype">void&#160;</td>
 261           <td class="paramname"></td><td>)</td>
 262           <td></td>
 263         </tr>
 264       </table>
 265 </div><div class="memdoc">
 266
 267 <p>Get ACTLR. </p>
 268 <dl class="section return"><dt>Returns</dt><dd>Auxiliary Control register value</dd></dl>
 269 <p>This function returns the value of the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
 270
 271 </div>
 272 </div>
 273 <a id="ga6317030a08c8c015425ffd0e3e7dae17" name="ga6317030a08c8c015425ffd0e3e7dae17"></a>
 274 <h2 class="memtitle"><span class="permalink"><a href="#ga6317030a08c8c015425ffd0e3e7dae17">&#9670;&#160;</a></span>__set_ACTLR()</h2>
 275
 276 <div class="memitem">
 277 <div class="memproto">
 278       <table class="memname">
 279         <tr>
 280           <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void __set_ACTLR </td>
 281           <td>(</td>
 282           <td class="paramtype">uint32_t&#160;</td>
 283           <td class="paramname"><em>actlr</em></td><td>)</td>
 284           <td></td>
 285         </tr>
 286       </table>
 287 </div><div class="memdoc">
 288
 289 <p>Set ACTLR. </p>
 290 <dl class="params"><dt>Parameters</dt><dd>
 291   <table class="params">
 292     <tr><td class="paramdir">[in]</td><td class="paramname">actlr</td><td>Auxiliary Control value to set</td></tr>
 293   </table>
 294   </dd>
 295 </dl>
 296 <p>This function assigns the given value to the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
 297
 298 </div>
 299 </div>
 300 </div><!-- contents -->
 301 </div><!-- doc-content -->
 302 <!-- start footer part -->
 303 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
 304   <ul>
 305     <li class="footer">
 306       <script type="text/javascript">
 307         <!--
 308         writeFooter.call(this);
 309         //-->
 310       </script>
 311     </li>
 312   </ul>
 313 </div>
 314 </body>
 315 </html>