The Device Header File <device.h> contains the following sections that are device specific:

Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
Configuration of the Processor and Core Peripherals reflect the features of the device.
Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

Interrupt Number Definition

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

Negative IRQn values represent processor core exceptions (internal interrupts).
Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s (deprecated).

Example:

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

typedef enum IRQn
{
/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
  NonMaskableInt_IRQn           = -14,      
  HardFault_IRQn                = -13,      
  SVCall_IRQn                   = -5,       
  PendSV_IRQn                   = -2,       
  SysTick_IRQn                  = -1,       
/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
  WAKEUP0_IRQn                  = 0,        
  WAKEUP1_IRQn                  = 1,        
  WAKEUP2_IRQn                  = 2,
                 :       :
                 :       :
  EINT1_IRQn                    = 30,       
  EINT0_IRQn                    = 31,       
} IRQn_Type;

Configuration of the Processor and Core Peripherals

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used. core_cm0.h

#define	Value Range	Default	Description
__CM0_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_cm0plus.h

#define	Value Range	Default	Description
__CM0PLUS_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT	0 .. 1	0	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_cm3.h

#define	Value Range	Default	Description
__CM3_REV	0x0101 \| 0x0200	0x0200	Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_cm4.h

#define	Value Range	Default	Description
__CM4_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_cm7.h

#define	Value Range	Default	Description
__CM7_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not.
__FPU_DP	0 .. 1	0	The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT	0 .. 1	1	Instruction Chache present or not
__DCACHE_PRESENT	0 .. 1	1	Data Chache present or not
__DTCM_PRESENT	0 .. 1	1	Data Tightly Coupled Memory is present or not

core_sc000.h

#define	Value Range	Default	Description
__SC000_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT	0 .. 1	0	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_sc300.h

#define	Value Range	Default	Description
__SC300_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	4	Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_CM23.h or core_ARMv8MBL.h

#define	Value Range	Default	Description
__ARMv8MBL_REV or __CM23_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__SAUREGION_PRESENT	0 .. 1	0	Defines if SAU regions are present or not
__VTOR_PRESENT	0 .. 1	0	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2	2	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_CM33.h or core_cm35p.h or core_ARMv8MML.h

#define	Value Range	Default	Description
__ARMv8MML_REV or __CM33_REV or __CM35P_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__SAUREGION_PRESENT	0 .. 1	0	Defines if SAU regions are present or not
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	3	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_CM55.h or core_ARMv81MML.h

#define	Value Range	Default	Description
__ARMv81MML_REV or __CM55_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__SAUREGION_PRESENT	0 .. 1	0	Defines if SAU regions are present or not
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not
__FPU_DP	0 .. 1	0	The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT	0 .. 1	1	Instruction Chache present or not
__DCACHE_PRESENT	0 .. 1	1	Data Chache present or not
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	3	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

core_CM85.h

#define	Value Range	Default	Description
__CM85_REV	0x0001	0x0001	Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT	0 .. 1	0	Defines if a MPU is present or not
__SAUREGION_PRESENT	0 .. 1	0	Defines if SAU regions are present or not
__FPU_PRESENT	0 .. 1	0	Defines if a FPU is present or not
__FPU_DP	0 .. 1	0	The combination of the defines __FPU_PRESENT and __FPU_DP determine whether the FPU is with single or double precision.
__ICACHE_PRESENT	0 .. 1	1	Instruction Chache present or not
__DCACHE_PRESENT	0 .. 1	1	Data Chache present or not
__VTOR_PRESENT	0 .. 1	1	Defines if a VTOR register is present or not
__NVIC_PRIO_BITS	2 .. 8	3	Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig	0 .. 1	0	Vendor defined SysTick_Config function.

Example

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

#define __CM4_REV                 0x0001U   /* Core revision r0p1                                 */
#define __MPU_PRESENT             1U        /* MPU present or not                                 */
#define __VTOR_PRESENT            1U        /* VTOR present */
#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels            */
#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used       */
#define __FPU_PRESENT             1U        /* FPU present or not                                 */
.
.
#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */
#include "system_<device>.h"                /* Device System Header                               */

CMSIS Version and Processor Information

Defines in the core_cpu.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

core_cm0.h

#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM0_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */
 
#define __CORTEX_M                (0U)                                              /* Cortex-M Core */

core_cm0plus.h

#define __CM0PLUS_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                     /* [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                      /* [15:0]  CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION       ((__CM0P_CMSIS_VERSION_MAIN << 16U) | \
                                        __CM0P_CMSIS_VERSION_SUB          )         /* CMSIS HAL version number */
 
#define __CORTEX_M                    (0U)                                          /* Cortex-M Core */

core_cm1.h

#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         
#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          
#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM1_CMSIS_VERSION_SUB           )             
#define __CORTEX_M                (1U)                                              

core_cm3.h

#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM3_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */
 
#define __CORTEX_M                (3U)                                              /* Cortex-M Core */

core_cm4.h

#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM4_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */
 
#define __CORTEX_M                (4U)                                              /* Cortex-M Core */

core_cm7.h

#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN                          /* [31:16] CMSIS HAL main version */
#define __CM7_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */
#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM7_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */
 
#define __CORTEX_M                (7U)                                              /* Cortex-M Core */

core_cm23.h

#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */
#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */
#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
                                     __CM23_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */
 
#define __CORTEX_M                (23U)                                             /* Cortex-M Core */

core_cm33.h

#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */
#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */
#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
                                     __CM33_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */
 
#define __CORTEX_M                (33U)                                             /* Cortex-M Core */

core_cm55.h

#define __CM55_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */
#define __CM55_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */
#define __CM55_CMSIS_VERSION       ((__CM55_CMSIS_VERSION_MAIN << 16U) | \
                                     __CM55_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */
 
#define __CORTEX_M                (7U)                                              /* Cortex-M Core */

core_sc000.h

#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
                                      __SC000_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */
 
#define __CORTEX_SC                 (0U)                                            /* Cortex secure core */

core_sc300.h

#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
                                      __SC300_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */
 
#define __CORTEX_SC                 (300U)                                          /* Cortex secure core */

core_cm35p.h

#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */
#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */
#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
                                      __CM35P_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */
 
#define __CORTEX_M                (35U)                                             /* Cortex-M Core */

core_ARMv8MBL.h

#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    /* [31:16] CMSIS HAL main version */
#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     /* [15:0]  CMSIS HAL sub version */
#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
                                         __ARMv8MBL_CMSIS_VERSION_SUB           )   /* CMSIS HAL version number */
 
#define __CORTEX_M                     (2U)                                         /* Cortex secure core */

core_ARMv8MML.h

#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    /* [31:16] CMSIS HAL main version */
#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     /* [15:0]  CMSIS HAL sub version */
#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
                                         __ARMv8MML_CMSIS_VERSION_SUB           )   /* CMSIS HAL version number */
 
#define __CORTEX_M                     (80U)                                        /* Cortex secure core */

Device Peripheral Access Layer

The Device Header File <device.h> contains for each peripheral:

Register Layout Typedef
Base Address
Access Definitions

The section Peripheral Access shows examples for peripheral definitions.

Device.h Template File

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.