The Device Header File <device.h> contains the following sections that are device specific:

Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
Configuration of the Processor and Core Peripherals reflect the features of the device.
Device Peripheral Access Layer definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
Access Functions for Peripherals (optioal) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.

Interrupt Number Definition

Configuration of the Processor and Core Peripherals

Device Peripheral Access Layer

The Device Header File <device.h> contains the following sections that are device specific:

Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
Configuration of the Processor and Core Peripherals reflect the features of the device.
Device Peripheral Access Layer definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

Interrupt Number Definition

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device. For devices implementing an Arm GIC these are defined as:

IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.

Example:

The following example shows the extension of the interrupt vector table for Cortex-A9 class device.

typedef enum IRQn
{
/******  SGI Interrupts Numbers                 ****************************************/
  SGI0_IRQn            =  0,      
  SGI1_IRQn            =  1,
  SGI2_IRQn            =  2,
       :                  :
  SGI15_IRQn           = 15,
 
/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
  GlobalTimer_IRQn     = 27,        
  PrivTimer_IRQn       = 29,        
  PrivWatchdog_IRQn    = 30,        
/******  Platform Exceptions Numbers ***************************************************/
  Watchdog_IRQn        = 32,        
  Timer0_IRQn          = 34,        
  Timer1_IRQn          = 35,        
  RTClock_IRQn         = 36,        
  UART0_IRQn           = 37,        
       :                  :
       :                  :
} IRQn_Type;

Configuration of the Processor and Core Peripherals

The Device Header File <device.h> configures the Cortex-A processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

#define	Value Range	Default	Description
__CM0_REV	0x0000	0x0000	Core revision number ([15:8] revision number, [7:0] patch number)
__CORTEX_A	5, 7, 9	(n/a)	Core type number
__FPU_PRESENT	0 .. 1	0	Defines if an FPU is present or not
__GIC_PRESENT	0 ..1	Defines if an GIC is present or not	Core revision number ([15:8] revision number, [7:0] patch number)
__TIM_PRESENT	0 .. 1	0	Defines if a private timer is present or not
__L2C_PRESENT	0 .. 1	0	Defines if a level 2 cache controller is present or not

Example

The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.

#define __CA_REV        0x0000U    
#define __CORTEX_A           9U    
#define __FPU_PRESENT        1U    
#define __GIC_PRESENT        1U    
#define __TIM_PRESENT        0U    
#define __L2C_PRESENT        0U    
:
:
#include "core_ca.h"               /* Cortex-A processor and core peripherals       */

CMSIS Version and Processor Information

Defines in the core_cpu.h file identify the version of the CMSIS-Core-A and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

#define __CA_CMSIS_VERSION_MAIN  (5U)                                 /* [31:16] CMSIS Core main version */
#define __CA_CMSIS_VERSION_SUB   (0U)                                 /* [15:0]  CMSIS Core sub version */
#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \
                                   __CA_CMSIS_VERSION_SUB          )  /* CMSIS Core version number */

Device Peripheral Access Layer

The Device Header File <device.h> contains for each peripheral:

Register Layout Typedef
Base Address
Access Definitions

The section Peripheral Access shows examples for peripheral definitions.

Device.h Template File

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.