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Core(M): Fix endless loop issue with non-optimized IAR builds
authorThomas Törnblom <thomas.tornblom@iar.com>
Tue, 4 Apr 2023 07:36:16 +0000 (09:36 +0200)
committerGitHub <noreply@github.com>
Tue, 4 Apr 2023 07:36:16 +0000 (09:36 +0200)
commit61030ff84a2a2cf875dab5feae2a82373486c096
treea053d6d1a5b97c1b0c66904ab72159042e1548aatree | snapshot
parent241b9d3b5e027c5839399e7b250d59d4f2ef6aa1commit | diff
Core(M): Fix endless loop issue with non-optimized IAR builds

This is an IAR fix for the problem described in
https://github.com/ARM-software/CMSIS_5/issues/620

IAR builds can not align the stack to the cache line size and
thus the invalidation is done in separate steps for the three
variables.

Fix validated on STM32H7 HW.

Signed-off-by: Thomas Törnblom <thomas.tornblom@iar.com>
Co-authored-by: Jonatan Antoni <jonatan.antoni@arm.com>
CMSIS/Core/Include/cachel1_armv7.h diff | blob | history
https://github.com/ARM-software/CMSIS_6.git