2 * FreeRTOS Kernel <DEVELOPMENT BRANCH>
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5 * SPDX-License-Identifier: MIT
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
36 /*-----------------------------------------------------------
37 * Port specific definitions.
39 * The settings in this file configure FreeRTOS correctly for the given hardware
42 * These settings should not be altered.
43 *-----------------------------------------------------------
46 /* Type definitions. */
48 #define portFLOAT float
49 #define portDOUBLE double
51 #define portSHORT short
52 #define portSTACK_TYPE uint32_t
53 #define portBASE_TYPE long
55 typedef portSTACK_TYPE StackType_t;
56 typedef long BaseType_t;
57 typedef unsigned long UBaseType_t;
59 typedef uint32_t TickType_t;
60 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
62 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
63 not need to be guarded with a critical section. */
64 #define portTICK_TYPE_IS_ATOMIC 1
66 /*-----------------------------------------------------------*/
68 /* Hardware specifics. */
69 #define portSTACK_GROWTH ( -1 )
70 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
71 #define portBYTE_ALIGNMENT 8
73 /*-----------------------------------------------------------*/
77 /* Called at the end of an ISR that can cause a context switch. */
78 #define portEND_SWITCHING_ISR( xSwitchRequired )\
80 extern uint32_t ulPortYieldRequired; \
82 if( xSwitchRequired != pdFALSE ) \
84 ulPortYieldRequired = pdTRUE; \
88 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
89 #define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
92 /*-----------------------------------------------------------
93 * Critical section control
94 *----------------------------------------------------------*/
96 extern void vPortEnterCritical( void );
97 extern void vPortExitCritical( void );
98 extern uint32_t ulPortSetInterruptMask( void );
99 extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
100 extern void vPortInstallFreeRTOSVectorTable( void );
102 /* These macros do not globally disable/enable interrupts. They do mask off
103 interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
104 #define portENTER_CRITICAL() vPortEnterCritical();
105 #define portEXIT_CRITICAL() vPortExitCritical();
106 #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
107 #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 )
108 #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
109 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
111 /*-----------------------------------------------------------*/
113 /* Task function macros as described on the FreeRTOS.org WEB site. These are
114 not required for this port but included in case common demo code that uses these
116 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
117 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
119 /* Prototype of the FreeRTOS tick handler. This must be installed as the
120 handler for whichever peripheral is used to generate the RTOS tick. */
121 void FreeRTOS_Tick_Handler( void );
123 /* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
124 created without an FPU context and must call vPortTaskUsesFPU() to give
125 themselves an FPU context before using any FPU instructions. If
126 configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
128 #if( configUSE_TASK_FPU_SUPPORT != 2 )
129 void vPortTaskUsesFPU( void );
131 /* Each task has an FPU context already, so define this function away to
132 nothing to prevent it being called accidentally. */
133 #define vPortTaskUsesFPU()
135 #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
137 #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
138 #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
140 /* Architecture specific optimisations. */
141 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
142 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
145 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
147 /* Store/clear the ready priorities in a bit map. */
148 #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
149 #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
151 /*-----------------------------------------------------------*/
153 #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
155 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
158 void vPortValidateInterruptPriority( void );
159 #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
160 #endif /* configASSERT */
162 #define portNOP() __asm volatile( "NOP" )
163 #define portINLINE __inline
170 /* The number of bits to shift for an interrupt priority is dependent on the
171 number of bits implemented by the interrupt controller. */
172 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
173 #define portPRIORITY_SHIFT 4
174 #define portMAX_BINARY_POINT_VALUE 3
175 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
176 #define portPRIORITY_SHIFT 3
177 #define portMAX_BINARY_POINT_VALUE 2
178 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
179 #define portPRIORITY_SHIFT 2
180 #define portMAX_BINARY_POINT_VALUE 1
181 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
182 #define portPRIORITY_SHIFT 1
183 #define portMAX_BINARY_POINT_VALUE 0
184 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
185 #define portPRIORITY_SHIFT 0
186 #define portMAX_BINARY_POINT_VALUE 0
188 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
191 /* Interrupt controller access addresses. */
192 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
193 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
194 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
195 #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
196 #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
198 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
199 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
200 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
201 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
202 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
203 #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
204 #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
206 #define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
208 #endif /* PORTMACRO_H */