begriffs open source - freertos/blob - portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c

   1 /*
   2  * FreeRTOS SMP Kernel V202110.00
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   6  * this software and associated documentation files (the "Software"), to deal in
   7  * the Software without restriction, including without limitation the rights to
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
   9  * the Software, and to permit persons to whom the Software is furnished to do so,
  10  * subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * https://www.FreeRTOS.org
  23  * https://github.com/FreeRTOS
  24  *
  25  * 1 tab == 4 spaces!
  26  */
  27
  28 /* Standard includes. */
  29 #include <stdint.h>
  30
  31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  32  * is defined correctly and privileged functions are placed in correct sections. */
  33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  34
  35 /* Portasm includes. */
  36 #include "portasm.h"
  37
  38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  39  * header files. */
  40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  41
  42 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  43 {
  44     __asm volatile
  45     (
  46         "       .syntax unified                                                                 \n"
  47         "                                                                                                       \n"
  48         "       ldr  r2, pxCurrentTCBConst2                                             \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  49         "       ldr  r1, [r2]                                                                   \n"/* Read pxCurrentTCB. */
  50         "       ldr  r0, [r1]                                                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
  51         "                                                                                                       \n"
  52         #if ( configENABLE_MPU == 1 )
  53             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */
  54             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
  55             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */
  56             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
  57             "   str r4, [r2]                                                                    \n"/* Disable MPU. */
  58             "                                                                                                   \n"
  59             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
  60             "   ldr  r3, [r1]                                                                   \n"/* r3 = *r1 i.e. r3 = MAIR0. */
  61             "   ldr  r2, xMAIR0Const2                                                   \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
  62             "   str  r3, [r2]                                                                   \n"/* Program MAIR0. */
  63             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */
  64             "   movs r3, #4                                                                             \n"/* r3 = 4. */
  65             "   str  r3, [r2]                                                                   \n"/* Program RNR = 4. */
  66             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
  67             "   ldr  r2, xRBARConst2                                                    \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
  68             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
  69             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
  70             "                                                                                                   \n"
  71             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
  72             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */
  73             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
  74             "   str r4, [r2]                                                                    \n"/* Enable MPU. */
  75             "   dsb                                                                                             \n"/* Force memory writes before continuing. */
  76         #endif /* configENABLE_MPU */
  77         "                                                                                                       \n"
  78         #if ( configENABLE_MPU == 1 )
  79             "   ldm  r0!, {r1-r3}                                                               \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
  80             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */
  81             "   msr  control, r2                                                                \n"/* Set this task's CONTROL value. */
  82             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */
  83             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */
  84             "   isb                                                                                             \n"
  85             "   mov  r0, #0                                                                             \n"
  86             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */
  87             "   bx   r3                                                                                 \n"/* Finally, branch to EXC_RETURN. */
  88         #else /* configENABLE_MPU */
  89             "   ldm  r0!, {r1-r2}                                                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
  90             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */
  91             "   movs r1, #2                                                                             \n"/* r1 = 2. */
  92             "   msr  CONTROL, r1                                                                \n"/* Switch to use PSP in the thread mode. */
  93             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */
  94             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */
  95             "   isb                                                                                             \n"
  96             "   mov  r0, #0                                                                             \n"
  97             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */
  98             "   bx   r2                                                                                 \n"/* Finally, branch to EXC_RETURN. */
  99         #endif /* configENABLE_MPU */
 100         "                                                                                                       \n"
 101         "       .align 4                                                                                \n"
 102         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"
 103         #if ( configENABLE_MPU == 1 )
 104             "xMPUCTRLConst2: .word 0xe000ed94                                   \n"
 105             "xMAIR0Const2: .word 0xe000edc0                                             \n"
 106             "xRNRConst2: .word 0xe000ed98                                               \n"
 107             "xRBARConst2: .word 0xe000ed9c                                              \n"
 108         #endif /* configENABLE_MPU */
 109     );
 110 }
 111 /*-----------------------------------------------------------*/
 112
 113 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 114 {
 115     __asm volatile
 116     (
 117         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */
 118         "       tst r0, #1                                                                              \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
 119         "       ite ne                                                                                  \n"
 120         "       movne r0, #0                                                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 121         "       moveq r0, #1                                                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 122         "       bx lr                                                                                   \n"/* Return. */
 123         "                                                                                                       \n"
 124         "       .align 4                                                                                \n"
 125         ::: "r0", "memory"
 126     );
 127 }
 128 /*-----------------------------------------------------------*/
 129
 130 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 131 {
 132     __asm volatile
 133     (
 134         "       mrs  r0, control                                                                \n"/* Read the CONTROL register. */
 135         "       bic r0, #1                                                                              \n"/* Clear the bit 0. */
 136         "       msr  control, r0                                                                \n"/* Write back the new CONTROL value. */
 137         "       bx lr                                                                                   \n"/* Return to the caller. */
 138         ::: "r0", "memory"
 139     );
 140 }
 141 /*-----------------------------------------------------------*/
 142
 143 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 144 {
 145     __asm volatile
 146     (
 147         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */
 148         "       orr r0, #1                                                                              \n"/* r0 = r0 | 1. */
 149         "       msr control, r0                                                                 \n"/* CONTROL = r0. */
 150         "       bx lr                                                                                   \n"/* Return to the caller. */
 151         ::: "r0", "memory"
 152     );
 153 }
 154 /*-----------------------------------------------------------*/
 155
 156 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 157 {
 158     __asm volatile
 159     (
 160         "       ldr r0, xVTORConst                                                              \n"/* Use the NVIC offset register to locate the stack. */
 161         "       ldr r0, [r0]                                                                    \n"/* Read the VTOR register which gives the address of vector table. */
 162         "       ldr r0, [r0]                                                                    \n"/* The first entry in vector table is stack pointer. */
 163         "       msr msp, r0                                                                             \n"/* Set the MSP back to the start of the stack. */
 164         "       cpsie i                                                                                 \n"/* Globally enable interrupts. */
 165         "       cpsie f                                                                                 \n"
 166         "       dsb                                                                                             \n"
 167         "       isb                                                                                             \n"
 168         "       svc %0                                                                                  \n"/* System call to start the first task. */
 169         "       nop                                                                                             \n"
 170         "                                                                                                       \n"
 171         "   .align 4                                                                            \n"
 172         "xVTORConst: .word 0xe000ed08                                           \n"
 173         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 174     );
 175 }
 176 /*-----------------------------------------------------------*/
 177
 178 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 179 {
 180     __asm volatile
 181     (
 182         "       mrs r0, basepri                                                                 \n"/* r0 = basepri. Return original basepri value. */
 183         "       mov r1, %0                                                                              \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 184         "       msr basepri, r1                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 185         "       dsb                                                                                             \n"
 186         "       isb                                                                                             \n"
 187         "       bx lr                                                                                   \n"/* Return. */
 188         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 189     );
 190 }
 191 /*-----------------------------------------------------------*/
 192
 193 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 194 {
 195     __asm volatile
 196     (
 197         "       msr basepri, r0                                                                 \n"/* basepri = ulMask. */
 198         "       dsb                                                                                             \n"
 199         "       isb                                                                                             \n"
 200         "       bx lr                                                                                   \n"/* Return. */
 201         ::: "memory"
 202     );
 203 }
 204 /*-----------------------------------------------------------*/
 205
 206 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 207 {
 208     __asm volatile
 209     (
 210         "       .syntax unified                                                                 \n"
 211         "                                                                                                       \n"
 212         "       mrs r0, psp                                                                             \n"/* Read PSP in r0. */
 213         #if ( configENABLE_FPU == 1 )
 214             "   tst lr, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 215             "   it eq                                                                                   \n"
 216             "   vstmdbeq r0!, {s16-s31}                                                 \n"/* Store the FPU registers which are not saved automatically. */
 217         #endif /* configENABLE_FPU */
 218         #if ( configENABLE_MPU == 1 )
 219             "   mrs r1, psplim                                                                  \n"/* r1 = PSPLIM. */
 220             "   mrs r2, control                                                                 \n"/* r2 = CONTROL. */
 221             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */
 222             "   stmdb r0!, {r1-r11}                                                             \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
 223         #else /* configENABLE_MPU */
 224             "   mrs r2, psplim                                                                  \n"/* r2 = PSPLIM. */
 225             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */
 226             "   stmdb r0!, {r2-r11}                                                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
 227         #endif /* configENABLE_MPU */
 228         "                                                                                                       \n"
 229         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 230         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */
 231         "       str r0, [r1]                                                                    \n"/* Save the new top of stack in TCB. */
 232         "                                                                                                       \n"
 233         "       mov r0, %0                                                                              \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 234         "       msr basepri, r0                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 235         "       dsb                                                                                             \n"
 236         "       isb                                                                                             \n"
 237         "       bl vTaskSwitchContext                                                   \n"
 238         "       mov r0, #0                                                                              \n"/* r0 = 0. */
 239         "       msr basepri, r0                                                                 \n"/* Enable interrupts. */
 240         "                                                                                                       \n"
 241         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 242         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */
 243         "       ldr r0, [r1]                                                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 244         "                                                                                                       \n"
 245         #if ( configENABLE_MPU == 1 )
 246             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */
 247             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
 248             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */
 249             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
 250             "   str r4, [r2]                                                                    \n"/* Disable MPU. */
 251             "                                                                                                   \n"
 252             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
 253             "   ldr r3, [r1]                                                                    \n"/* r3 = *r1 i.e. r3 = MAIR0. */
 254             "   ldr r2, xMAIR0Const                                                             \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
 255             "   str r3, [r2]                                                                    \n"/* Program MAIR0. */
 256             "   ldr r2, xRNRConst                                                               \n"/* r2 = 0xe000ed98 [Location of RNR]. */
 257             "   movs r3, #4                                                                             \n"/* r3 = 4. */
 258             "   str r3, [r2]                                                                    \n"/* Program RNR = 4. */
 259             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
 260             "   ldr r2, xRBARConst                                                              \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
 261             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
 262             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
 263             "                                                                                                   \n"
 264             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
 265             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */
 266             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
 267             "   str r4, [r2]                                                                    \n"/* Enable MPU. */
 268             "   dsb                                                                                             \n"/* Force memory writes before continuing. */
 269         #endif /* configENABLE_MPU */
 270         "                                                                                                       \n"
 271         #if ( configENABLE_MPU == 1 )
 272             "   ldmia r0!, {r1-r11}                                                             \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
 273         #else /* configENABLE_MPU */
 274             "   ldmia r0!, {r2-r11}                                                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 275         #endif /* configENABLE_MPU */
 276         "                                                                                                       \n"
 277         #if ( configENABLE_FPU == 1 )
 278             "   tst r3, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 279             "   it eq                                                                                   \n"
 280             "   vldmiaeq r0!, {s16-s31}                                                 \n"/* Restore the FPU registers which are not restored automatically. */
 281         #endif /* configENABLE_FPU */
 282         "                                                                                                       \n"
 283         #if ( configENABLE_MPU == 1 )
 284             "   msr psplim, r1                                                                  \n"/* Restore the PSPLIM register value for the task. */
 285             "   msr control, r2                                                                 \n"/* Restore the CONTROL register value for the task. */
 286         #else /* configENABLE_MPU */
 287             "   msr psplim, r2                                                                  \n"/* Restore the PSPLIM register value for the task. */
 288         #endif /* configENABLE_MPU */
 289         "       msr psp, r0                                                                             \n"/* Remember the new top of stack for the task. */
 290         "       bx r3                                                                                   \n"
 291         "                                                                                                       \n"
 292         "       .align 4                                                                                \n"
 293         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"
 294         #if ( configENABLE_MPU == 1 )
 295             "xMPUCTRLConst: .word 0xe000ed94                                    \n"
 296             "xMAIR0Const: .word 0xe000edc0                                              \n"
 297             "xRNRConst: .word 0xe000ed98                                                \n"
 298             "xRBARConst: .word 0xe000ed9c                                               \n"
 299         #endif /* configENABLE_MPU */
 300         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 301     );
 302 }
 303 /*-----------------------------------------------------------*/
 304
 305 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 306 {
 307     __asm volatile
 308     (
 309         "       tst lr, #4                                                                              \n"
 310         "       ite eq                                                                                  \n"
 311         "       mrseq r0, msp                                                                   \n"
 312         "       mrsne r0, psp                                                                   \n"
 313         "       ldr r1, svchandler_address_const                                \n"
 314         "       bx r1                                                                                   \n"
 315         "                                                                                                       \n"
 316         "       .align 4                                                                                \n"
 317         "svchandler_address_const: .word vPortSVCHandler_C      \n"
 318     );
 319 }
 320 /*-----------------------------------------------------------*/