2 * FreeRTOS SMP Kernel V202110.00
3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
6 * this software and associated documentation files (the "Software"), to deal in
7 * the Software without restriction, including without limitation the rights to
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
9 * the Software, and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * https://www.FreeRTOS.org
23 * https://github.com/FreeRTOS
28 /* Kernel includes. */
31 /* Machine includes */
33 #include <machine/intrinsics.h>
34 #include <machine/cint.h>
35 /*---------------------------------------------------------------------------*/
38 * This reference is required by the Save/Restore Context Macros.
40 extern volatile uint32_t *pxCurrentTCB;
41 /*-----------------------------------------------------------*/
44 * This file contains base definitions for all of the possible traps in the system.
45 * It is suggested to provide implementations for all of the traps but for
46 * the time being they simply trigger a DEBUG instruction so that it is easy
47 * to see what caused a particular trap.
49 * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
52 /* The Trap Classes. */
53 #define portMMU_TRAP 0
54 #define portIPT_TRAP 1
57 #define portSBP_TRAP 4
58 #define portASSERT_TRAP 5
59 #define portNMI_TRAP 7
61 /* MMU Trap Identifications. */
62 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
63 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
65 /* Internal Protection Trap Identifications. */
66 #define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
67 #define portTIN_IPT_MEMORY_PROTECTION_READ 2
68 #define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
69 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
70 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
71 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
72 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
74 /* Instruction Error Trap Identifications. */
75 #define portTIN_IE_ILLEGAL_OPCODE 1
76 #define portTIN_IE_UNIMPLEMENTED_OPCODE 2
77 #define portTIN_IE_INVALID_OPERAND 3
78 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
79 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
81 /* Context Management Trap Identifications. */
82 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
83 #define portTIN_CM_CALL_DEPTH_OVERFLOW 2
84 #define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
85 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
86 #define portTIN_CM_CALL_STACK_UNDERFLOW 5
87 #define portTIN_CM_CONTEXT_TYPE 6
88 #define portTIN_CM_NESTING_ERROR 7
90 /* System Bus and Peripherals Trap Identifications. */
91 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
92 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
93 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
94 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
95 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
96 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
98 /* Assertion Trap Identifications. */
99 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
100 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
102 /* Non-maskable Interrupt Trap Identifications. */
103 #define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
104 /*---------------------------------------------------------------------------*/
106 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
107 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
108 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
109 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
110 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
111 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
112 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
113 /*---------------------------------------------------------------------------*/
115 void vTrapInstallHandlers( void )
117 if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
122 if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
127 if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
132 if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
137 if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
142 if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
147 if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
152 /*-----------------------------------------------------------*/
154 void vMMUTrap( int iTrapIdentification )
156 switch( iTrapIdentification )
158 case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
159 case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
165 /*---------------------------------------------------------------------------*/
167 void vInternalProtectionTrap( int iTrapIdentification )
169 /* Deliberate fall through to default. */
170 switch( iTrapIdentification )
172 case portTIN_IPT_PRIVILIGED_INSTRUCTION:
173 /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
175 case portTIN_IPT_MEMORY_PROTECTION_READ:
176 /* Load word using invalid address. */
178 case portTIN_IPT_MEMORY_PROTECTION_WRITE:
179 /* Store Word using invalid address. */
181 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
182 /* PC jumped to an address outside of the valid range. */
184 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
185 /* Access to a peripheral denied at current execution level. */
187 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
190 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
191 /* Tried to modify a global address pointer register. */
195 pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
200 /*---------------------------------------------------------------------------*/
202 void vInstructionErrorTrap( int iTrapIdentification )
204 /* Deliberate fall through to default. */
205 switch( iTrapIdentification )
207 case portTIN_IE_ILLEGAL_OPCODE:
208 case portTIN_IE_UNIMPLEMENTED_OPCODE:
209 case portTIN_IE_INVALID_OPERAND:
210 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
211 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
217 /*---------------------------------------------------------------------------*/
219 void vContextManagementTrap( int iTrapIdentification )
221 /* Deliberate fall through to default. */
222 switch( iTrapIdentification )
224 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
225 case portTIN_CM_CALL_DEPTH_OVERFLOW:
226 case portTIN_CM_CALL_DEPTH_UNDEFLOW:
227 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
228 case portTIN_CM_CALL_STACK_UNDERFLOW:
229 case portTIN_CM_CONTEXT_TYPE:
230 case portTIN_CM_NESTING_ERROR:
236 /*---------------------------------------------------------------------------*/
238 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
240 /* Deliberate fall through to default. */
241 switch( iTrapIdentification )
243 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
244 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
245 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
246 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
247 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
248 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
254 /*---------------------------------------------------------------------------*/
256 void vAssertionTrap( int iTrapIdentification )
258 /* Deliberate fall through to default. */
259 switch( iTrapIdentification )
261 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
262 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
268 /*---------------------------------------------------------------------------*/
270 void vNonMaskableInterruptTrap( int iTrapIdentification )
272 /* Deliberate fall through to default. */
273 switch( iTrapIdentification )
275 case portTIN_NMI_NON_MASKABLE_INTERRUPT:
281 /*---------------------------------------------------------------------------*/