begriffs open source - freertos/blob - portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>\r
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   8  * this software and associated documentation files (the "Software"), to deal in\r
   9  * the Software without restriction, including without limitation the rights to\r
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
  11  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  12  * subject to the following conditions:\r
  13  *\r
  14  * The above copyright notice and this permission notice shall be included in all\r
  15  * copies or substantial portions of the Software.\r
  16  *\r
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  23  *\r
  24  * https://www.FreeRTOS.org\r
  25  * https://github.com/FreeRTOS\r
  26  *\r
  27  */\r
  28 \r
  29 /* Standard includes. */\r
  30 #include <stdint.h>\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
  33  * is defined correctly and privileged functions are placed in correct sections. */\r
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  35 \r
  36 /* Portasm includes. */\r
  37 #include "portasm.h"\r
  38 \r
  39 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
  40  * header files. */\r
  41 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  42 \r
  43 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  44 {\r
  45     __asm volatile\r
  46     (\r
  47         "       .syntax unified                                                                 \n"\r
  48         "                                                                                                       \n"\r
  49         "       ldr  r2, pxCurrentTCBConst2                                             \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  50         "       ldr  r1, [r2]                                                                   \n"/* Read pxCurrentTCB. */\r
  51         "       ldr  r0, [r1]                                                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  52         "                                                                                                       \n"\r
  53         #if ( configENABLE_MPU == 1 )\r
  54             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
  55             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  56             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  57             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  58             "   str r4, [r2]                                                                    \n"/* Disable MPU. */\r
  59             "                                                                                                   \n"\r
  60             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  61             "   ldr  r3, [r1]                                                                   \n"/* r3 = *r1 i.e. r3 = MAIR0. */\r
  62             "   ldr  r2, xMAIR0Const2                                                   \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  63             "   str  r3, [r2]                                                                   \n"/* Program MAIR0. */\r
  64             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
  65             "   movs r3, #4                                                                             \n"/* r3 = 4. */\r
  66             "   str  r3, [r2]                                                                   \n"/* Program RNR = 4. */\r
  67             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  68             "   ldr  r2, xRBARConst2                                                    \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
  69             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 set of RBAR/RLAR registers from TCB. */\r
  70             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  71             "                                                                                                   \n"\r
  72             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  73             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  74             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
  75             "   str r4, [r2]                                                                    \n"/* Enable MPU. */\r
  76             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
  77         #endif /* configENABLE_MPU */\r
  78         "                                                                                                       \n"\r
  79         #if ( configENABLE_MPU == 1 )\r
  80             "   ldm  r0!, {r1-r3}                                                               \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
  81             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
  82             "   msr  control, r2                                                                \n"/* Set this task's CONTROL value. */\r
  83             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
  84             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
  85             "   isb                                                                                             \n"\r
  86             "   mov  r0, #0                                                                             \n"\r
  87             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */\r
  88             "   bx   r3                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
  89         #else /* configENABLE_MPU */\r
  90             "   ldm  r0!, {r1-r2}                                                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
  91             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
  92             "   movs r1, #2                                                                             \n"/* r1 = 2. */\r
  93             "   msr  CONTROL, r1                                                                \n"/* Switch to use PSP in the thread mode. */\r
  94             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
  95             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
  96             "   isb                                                                                             \n"\r
  97             "   mov  r0, #0                                                                             \n"\r
  98             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */\r
  99             "   bx   r2                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
 100         #endif /* configENABLE_MPU */\r
 101         "                                                                                                       \n"\r
 102         "       .align 4                                                                                \n"\r
 103         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 104         #if ( configENABLE_MPU == 1 )\r
 105             "xMPUCTRLConst2: .word 0xe000ed94                                   \n"\r
 106             "xMAIR0Const2: .word 0xe000edc0                                             \n"\r
 107             "xRNRConst2: .word 0xe000ed98                                               \n"\r
 108             "xRBARConst2: .word 0xe000ed9c                                              \n"\r
 109         #endif /* configENABLE_MPU */\r
 110     );\r
 111 }\r
 112 /*-----------------------------------------------------------*/\r
 113 \r
 114 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 115 {\r
 116     __asm volatile\r
 117     (\r
 118         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 119         "       tst r0, #1                                                                              \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 120         "       ite ne                                                                                  \n"\r
 121         "       movne r0, #0                                                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 122         "       moveq r0, #1                                                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 123         "       bx lr                                                                                   \n"/* Return. */\r
 124         "                                                                                                       \n"\r
 125         "       .align 4                                                                                \n"\r
 126         ::: "r0", "memory"\r
 127     );\r
 128 }\r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 132 {\r
 133     __asm volatile\r
 134     (\r
 135         "       mrs  r0, control                                                                \n"/* Read the CONTROL register. */\r
 136         "       bic r0, #1                                                                              \n"/* Clear the bit 0. */\r
 137         "       msr  control, r0                                                                \n"/* Write back the new CONTROL value. */\r
 138         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 139         ::: "r0", "memory"\r
 140     );\r
 141 }\r
 142 /*-----------------------------------------------------------*/\r
 143 \r
 144 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 145 {\r
 146     __asm volatile\r
 147     (\r
 148         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 149         "       orr r0, #1                                                                              \n"/* r0 = r0 | 1. */\r
 150         "       msr control, r0                                                                 \n"/* CONTROL = r0. */\r
 151         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 152         ::: "r0", "memory"\r
 153     );\r
 154 }\r
 155 /*-----------------------------------------------------------*/\r
 156 \r
 157 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 158 {\r
 159     __asm volatile\r
 160     (\r
 161         "       ldr r0, xVTORConst                                                              \n"/* Use the NVIC offset register to locate the stack. */\r
 162         "       ldr r0, [r0]                                                                    \n"/* Read the VTOR register which gives the address of vector table. */\r
 163         "       ldr r0, [r0]                                                                    \n"/* The first entry in vector table is stack pointer. */\r
 164         "       msr msp, r0                                                                             \n"/* Set the MSP back to the start of the stack. */\r
 165         "       cpsie i                                                                                 \n"/* Globally enable interrupts. */\r
 166         "       cpsie f                                                                                 \n"\r
 167         "       dsb                                                                                             \n"\r
 168         "       isb                                                                                             \n"\r
 169         "       svc %0                                                                                  \n"/* System call to start the first task. */\r
 170         "       nop                                                                                             \n"\r
 171         "                                                                                                       \n"\r
 172         "   .align 4                                                                            \n"\r
 173         "xVTORConst: .word 0xe000ed08                                           \n"\r
 174         ::"i" ( portSVC_START_SCHEDULER ) : "memory"\r
 175     );\r
 176 }\r
 177 /*-----------------------------------------------------------*/\r
 178 \r
 179 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 180 {\r
 181     __asm volatile\r
 182     (\r
 183         "       mrs r0, basepri                                                                 \n"/* r0 = basepri. Return original basepri value. */\r
 184         "       mov r1, %0                                                                              \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 185         "       msr basepri, r1                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 186         "       dsb                                                                                             \n"\r
 187         "       isb                                                                                             \n"\r
 188         "       bx lr                                                                                   \n"/* Return. */\r
 189         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
 190     );\r
 191 }\r
 192 /*-----------------------------------------------------------*/\r
 193 \r
 194 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 195 {\r
 196     __asm volatile\r
 197     (\r
 198         "       msr basepri, r0                                                                 \n"/* basepri = ulMask. */\r
 199         "       dsb                                                                                             \n"\r
 200         "       isb                                                                                             \n"\r
 201         "       bx lr                                                                                   \n"/* Return. */\r
 202         ::: "memory"\r
 203     );\r
 204 }\r
 205 /*-----------------------------------------------------------*/\r
 206 \r
 207 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 208 {\r
 209     __asm volatile\r
 210     (\r
 211         "       .syntax unified                                                                 \n"\r
 212         "                                                                                                       \n"\r
 213         "       mrs r0, psp                                                                             \n"/* Read PSP in r0. */\r
 214         #if ( configENABLE_FPU == 1 )\r
 215             "   tst lr, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 216             "   it eq                                                                                   \n"\r
 217             "   vstmdbeq r0!, {s16-s31}                                                 \n"/* Store the FPU registers which are not saved automatically. */\r
 218         #endif /* configENABLE_FPU */\r
 219         #if ( configENABLE_MPU == 1 )\r
 220             "   mrs r1, psplim                                                                  \n"/* r1 = PSPLIM. */\r
 221             "   mrs r2, control                                                                 \n"/* r2 = CONTROL. */\r
 222             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 223             "   stmdb r0!, {r1-r11}                                                             \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 224         #else /* configENABLE_MPU */\r
 225             "   mrs r2, psplim                                                                  \n"/* r2 = PSPLIM. */\r
 226             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 227             "   stmdb r0!, {r2-r11}                                                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
 228         #endif /* configENABLE_MPU */\r
 229         "                                                                                                       \n"\r
 230         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 231         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 232         "       str r0, [r1]                                                                    \n"/* Save the new top of stack in TCB. */\r
 233         "                                                                                                       \n"\r
 234         "       mov r0, %0                                                                              \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
 235         "       msr basepri, r0                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 236         "       dsb                                                                                             \n"\r
 237         "       isb                                                                                             \n"\r
 238         "       bl vTaskSwitchContext                                                   \n"\r
 239         "       mov r0, #0                                                                              \n"/* r0 = 0. */\r
 240         "       msr basepri, r0                                                                 \n"/* Enable interrupts. */\r
 241         "                                                                                                       \n"\r
 242         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 243         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 244         "       ldr r0, [r1]                                                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 245         "                                                                                                       \n"\r
 246         #if ( configENABLE_MPU == 1 )\r
 247             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
 248             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 249             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 250             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 251             "   str r4, [r2]                                                                    \n"/* Disable MPU. */\r
 252             "                                                                                                   \n"\r
 253             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 254             "   ldr r3, [r1]                                                                    \n"/* r3 = *r1 i.e. r3 = MAIR0. */\r
 255             "   ldr r2, xMAIR0Const                                                             \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 256             "   str r3, [r2]                                                                    \n"/* Program MAIR0. */\r
 257             "   ldr r2, xRNRConst                                                               \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
 258             "   movs r3, #4                                                                             \n"/* r3 = 4. */\r
 259             "   str r3, [r2]                                                                    \n"/* Program RNR = 4. */\r
 260             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 261             "   ldr r2, xRBARConst                                                              \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
 262             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 263             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 264             "                                                                                                   \n"\r
 265             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 266             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 267             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 268             "   str r4, [r2]                                                                    \n"/* Enable MPU. */\r
 269             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
 270         #endif /* configENABLE_MPU */\r
 271         "                                                                                                       \n"\r
 272         #if ( configENABLE_MPU == 1 )\r
 273             "   ldmia r0!, {r1-r11}                                                             \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 274         #else /* configENABLE_MPU */\r
 275             "   ldmia r0!, {r2-r11}                                                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 276         #endif /* configENABLE_MPU */\r
 277         "                                                                                                       \n"\r
 278         #if ( configENABLE_FPU == 1 )\r
 279             "   tst r3, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 280             "   it eq                                                                                   \n"\r
 281             "   vldmiaeq r0!, {s16-s31}                                                 \n"/* Restore the FPU registers which are not restored automatically. */\r
 282         #endif /* configENABLE_FPU */\r
 283         "                                                                                                       \n"\r
 284         #if ( configENABLE_MPU == 1 )\r
 285             "   msr psplim, r1                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 286             "   msr control, r2                                                                 \n"/* Restore the CONTROL register value for the task. */\r
 287         #else /* configENABLE_MPU */\r
 288             "   msr psplim, r2                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 289         #endif /* configENABLE_MPU */\r
 290         "       msr psp, r0                                                                             \n"/* Remember the new top of stack for the task. */\r
 291         "       bx r3                                                                                   \n"\r
 292         "                                                                                                       \n"\r
 293         "       .align 4                                                                                \n"\r
 294         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 295         #if ( configENABLE_MPU == 1 )\r
 296             "xMPUCTRLConst: .word 0xe000ed94                                    \n"\r
 297             "xMAIR0Const: .word 0xe000edc0                                              \n"\r
 298             "xRNRConst: .word 0xe000ed98                                                \n"\r
 299             "xRBARConst: .word 0xe000ed9c                                               \n"\r
 300         #endif /* configENABLE_MPU */\r
 301         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
 302     );\r
 303 }\r
 304 /*-----------------------------------------------------------*/\r
 305 \r
 306 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 307 {\r
 308     __asm volatile\r
 309     (\r
 310         "       tst lr, #4                                                                              \n"\r
 311         "       ite eq                                                                                  \n"\r
 312         "       mrseq r0, msp                                                                   \n"\r
 313         "       mrsne r0, psp                                                                   \n"\r
 314         "       ldr r1, svchandler_address_const                                \n"\r
 315         "       bx r1                                                                                   \n"\r
 316         "                                                                                                       \n"\r
 317         "       .align 4                                                                                \n"\r
 318         "svchandler_address_const: .word vPortSVCHandler_C      \n"\r
 319     );\r
 320 }\r
 321 /*-----------------------------------------------------------*/\r