begriffs open source - freertos/blob - portable/IAR/ARM_CM23/non_secure/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>\r
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   8  * this software and associated documentation files (the "Software"), to deal in\r
   9  * the Software without restriction, including without limitation the rights to\r
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
  11  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  12  * subject to the following conditions:\r
  13  *\r
  14  * The above copyright notice and this permission notice shall be included in all\r
  15  * copies or substantial portions of the Software.\r
  16  *\r
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  23  *\r
  24  * https://www.FreeRTOS.org\r
  25  * https://github.com/FreeRTOS\r
  26  *\r
  27  */\r
  28 \r
  29         EXTERN pxCurrentTCB\r
  30         EXTERN xSecureContext\r
  31         EXTERN vTaskSwitchContext\r
  32         EXTERN vPortSVCHandler_C\r
  33         EXTERN SecureContext_SaveContext\r
  34         EXTERN SecureContext_LoadContext\r
  35 \r
  36         PUBLIC xIsPrivileged\r
  37         PUBLIC vResetPrivilege\r
  38         PUBLIC vPortAllocateSecureContext\r
  39         PUBLIC vRestoreContextOfFirstTask\r
  40         PUBLIC vRaisePrivilege\r
  41         PUBLIC vStartFirstTask\r
  42         PUBLIC ulSetInterruptMask\r
  43         PUBLIC vClearInterruptMask\r
  44         PUBLIC PendSV_Handler\r
  45         PUBLIC SVC_Handler\r
  46         PUBLIC vPortFreeSecureContext\r
  47 \r
  48 #if ( configENABLE_FPU == 1 )\r
  49         #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
  50 #endif\r
  51 /*-----------------------------------------------------------*/\r
  52 \r
  53 /*---------------- Unprivileged Functions -------------------*/\r
  54 \r
  55 /*-----------------------------------------------------------*/\r
  56 \r
  57         SECTION .text:CODE:NOROOT(2)\r
  58         THUMB\r
  59 /*-----------------------------------------------------------*/\r
  60 \r
  61 xIsPrivileged:\r
  62         mrs r0, control                                                 /* r0 = CONTROL. */\r
  63         movs r1, #1                                                             /* r1 = 1. */\r
  64         tst r0, r1                                                              /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
  65         beq running_privileged                                  /* If the result of previous AND operation was 0, branch. */\r
  66         movs r0, #0                                                             /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  67         bx lr                                                                   /* Return. */\r
  68         running_privileged:\r
  69                 movs r0, #1                                                     /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
  70                 bx lr                                                           /* Return. */\r
  71 /*-----------------------------------------------------------*/\r
  72 \r
  73 vResetPrivilege:\r
  74         mrs r0, control                                                 /* r0 = CONTROL. */\r
  75         movs r1, #1                                                             /* r1 = 1. */\r
  76         orrs r0, r1                                                             /* r0 = r0 | r1. */\r
  77         msr control, r0                                                 /* CONTROL = r0. */\r
  78         bx lr                                                                   /* Return to the caller. */\r
  79 /*-----------------------------------------------------------*/\r
  80 \r
  81 vPortAllocateSecureContext:\r
  82         svc 0                                                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
  83         bx lr                                                                   /* Return. */\r
  84 /*-----------------------------------------------------------*/\r
  85 \r
  86 /*----------------- Privileged Functions --------------------*/\r
  87 \r
  88 /*-----------------------------------------------------------*/\r
  89 \r
  90         SECTION privileged_functions:CODE:NOROOT(2)\r
  91         THUMB\r
  92 /*-----------------------------------------------------------*/\r
  93 \r
  94 vRestoreContextOfFirstTask:\r
  95         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  96         ldr  r3, [r2]                                                   /* Read pxCurrentTCB. */\r
  97         ldr  r0, [r3]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  98 \r
  99 #if ( configENABLE_MPU == 1 )\r
 100         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
 101         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 102         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 103         movs r5, #1                                                             /* r5 = 1. */\r
 104         bics r4, r5                                                             /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
 105         str r4, [r2]                                                    /* Disable MPU. */\r
 106 \r
 107         adds r3, #4                                                             /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
 108         ldr  r4, [r3]                                                   /* r4 = *r3 i.e. r4 = MAIR0. */\r
 109         ldr  r2, =0xe000edc0                                    /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 110         str  r4, [r2]                                                   /* Program MAIR0. */\r
 111         ldr  r2, =0xe000ed98                                    /* r2 = 0xe000ed98 [Location of RNR]. */\r
 112         adds r3, #4                                                             /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
 113         movs r5, #4                                                             /* r5 = 4. */\r
 114         str  r5, [r2]                                                   /* Program RNR = 4. */\r
 115         ldmia r3!, {r6,r7}                                              /* Read first set of RBAR/RLAR from TCB. */\r
 116         ldr  r4, =0xe000ed9c                                    /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 117         stmia r4!, {r6,r7}                                              /* Write first set of RBAR/RLAR registers. */\r
 118         movs r5, #5                                                             /* r5 = 5. */\r
 119         str  r5, [r2]                                                   /* Program RNR = 5. */\r
 120         ldmia r3!, {r6,r7}                                              /* Read second set of RBAR/RLAR from TCB. */\r
 121         ldr  r4, =0xe000ed9c                                    /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 122         stmia r4!, {r6,r7}                                              /* Write second set of RBAR/RLAR registers. */\r
 123         movs r5, #6                                                             /* r5 = 6. */\r
 124         str  r5, [r2]                                                   /* Program RNR = 6. */\r
 125         ldmia r3!, {r6,r7}                                              /* Read third set of RBAR/RLAR from TCB. */\r
 126         ldr  r4, =0xe000ed9c                                    /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 127         stmia r4!, {r6,r7}                                              /* Write third set of RBAR/RLAR registers. */\r
 128         movs r5, #7                                                             /* r5 = 7. */\r
 129         str  r5, [r2]                                                   /* Program RNR = 7. */\r
 130         ldmia r3!, {r6,r7}                                              /* Read fourth set of RBAR/RLAR from TCB. */\r
 131         ldr  r4, =0xe000ed9c                                    /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 132         stmia r4!, {r6,r7}                                              /* Write fourth set of RBAR/RLAR registers. */\r
 133 \r
 134         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 135         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 136         movs r5, #1                                                             /* r5 = 1. */\r
 137         orrs r4, r5                                                             /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
 138         str r4, [r2]                                                    /* Enable MPU. */\r
 139         dsb                                                                             /* Force memory writes before continuing. */\r
 140 #endif /* configENABLE_MPU */\r
 141 \r
 142 #if ( configENABLE_MPU == 1 )\r
 143         ldm  r0!, {r1-r4}                                               /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
 144         ldr  r5, =xSecureContext\r
 145         str  r1, [r5]                                                   /* Set xSecureContext to this task's value for the same. */\r
 146         msr  psplim, r2                                                 /* Set this task's PSPLIM value. */\r
 147         msr  control, r3                                                /* Set this task's CONTROL value. */\r
 148         adds r0, #32                                                    /* Discard everything up to r0. */\r
 149         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 150         isb\r
 151         bx   r4                                                                 /* Finally, branch to EXC_RETURN. */\r
 152 #else /* configENABLE_MPU */\r
 153         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
 154         ldr  r4, =xSecureContext\r
 155         str  r1, [r4]                                                   /* Set xSecureContext to this task's value for the same. */\r
 156         msr  psplim, r2                                                 /* Set this task's PSPLIM value. */\r
 157         movs r1, #2                                                             /* r1 = 2. */\r
 158         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 159         adds r0, #32                                                    /* Discard everything up to r0. */\r
 160         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 161         isb\r
 162         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 163 #endif /* configENABLE_MPU */\r
 164 /*-----------------------------------------------------------*/\r
 165 \r
 166 vRaisePrivilege:\r
 167         mrs r0, control                                                 /* Read the CONTROL register. */\r
 168         movs r1, #1                                                             /* r1 = 1. */\r
 169         bics r0, r1                                                             /* Clear the bit 0. */\r
 170         msr control, r0                                                 /* Write back the new CONTROL value. */\r
 171         bx lr                                                                   /* Return to the caller. */\r
 172 /*-----------------------------------------------------------*/\r
 173 \r
 174 vStartFirstTask:\r
 175         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 176         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 177         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 178         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 179         cpsie i                                                                 /* Globally enable interrupts. */\r
 180         dsb\r
 181         isb\r
 182         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 183 /*-----------------------------------------------------------*/\r
 184 \r
 185 ulSetInterruptMask:\r
 186         mrs r0, PRIMASK\r
 187         cpsid i\r
 188         bx lr\r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 vClearInterruptMask:\r
 192         msr PRIMASK, r0\r
 193         bx lr\r
 194 /*-----------------------------------------------------------*/\r
 195 \r
 196 PendSV_Handler:\r
 197         mrs r1, psp                                                             /* Read PSP in r1. */\r
 198         ldr r2, =xSecureContext                                 /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 199         ldr r0, [r2]                                                    /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
 200 \r
 201         cbz r0, save_ns_context                                 /* No secure context to save. */\r
 202         push {r0-r2, r14}\r
 203         bl SecureContext_SaveContext\r
 204         pop {r0-r3}                                                             /* LR is now in r3. */\r
 205         mov lr, r3                                                              /* LR = r3. */\r
 206         lsls r2, r3, #25                                                /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 207         bpl save_ns_context                                             /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 208         ldr r3, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 209         ldr r2, [r3]                                                    /* Read pxCurrentTCB. */\r
 210 #if ( configENABLE_MPU == 1 )\r
 211         subs r1, r1, #16                                                /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 212         str r1, [r2]                                                    /* Save the new top of stack in TCB. */\r
 213         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 214         mrs r3, control                                                 /* r3 = CONTROL. */\r
 215         mov r4, lr                                                              /* r4 = LR/EXC_RETURN. */\r
 216         stmia r1!, {r0, r2-r4}                                  /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 217 #else /* configENABLE_MPU */\r
 218         subs r1, r1, #12                                                /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
 219         str r1, [r2]                                                    /* Save the new top of stack in TCB. */\r
 220         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 221         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 222         stmia r1!, {r0, r2-r3}                                  /* Store xSecureContext, PSPLIM and LR on the stack. */\r
 223 #endif /* configENABLE_MPU */\r
 224         b select_next_task\r
 225 \r
 226         save_ns_context:\r
 227                 ldr r3, =pxCurrentTCB                           /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 228                 ldr r2, [r3]                                            /* Read pxCurrentTCB. */\r
 229         #if ( configENABLE_MPU == 1 )\r
 230                 subs r1, r1, #48                                        /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
 231                 str r1, [r2]                                            /* Save the new top of stack in TCB. */\r
 232                 adds r1, r1, #16                                        /* r1 = r1 + 16. */\r
 233                 stmia r1!, {r4-r7}                                      /* Store the low registers that are not saved automatically. */\r
 234                 mov r4, r8                                                      /* r4 = r8. */\r
 235                 mov r5, r9                                                      /* r5 = r9. */\r
 236                 mov r6, r10                                                     /* r6 = r10. */\r
 237                 mov r7, r11                                                     /* r7 = r11. */\r
 238                 stmia r1!, {r4-r7}                                      /* Store the high registers that are not saved automatically. */\r
 239                 mrs r2, psplim                                          /* r2 = PSPLIM. */\r
 240                 mrs r3, control                                         /* r3 = CONTROL. */\r
 241                 mov r4, lr                                                      /* r4 = LR/EXC_RETURN. */\r
 242                 subs r1, r1, #48                                        /* r1 = r1 - 48. */\r
 243                 stmia r1!, {r0, r2-r4}                          /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 244         #else /* configENABLE_MPU */\r
 245                 subs r1, r1, #44                                        /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
 246                 str r1, [r2]                                            /* Save the new top of stack in TCB. */\r
 247                 mrs r2, psplim                                          /* r2 = PSPLIM. */\r
 248                 mov r3, lr                                                      /* r3 = LR/EXC_RETURN. */\r
 249                 stmia r1!, {r0, r2-r7}                          /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */\r
 250                 mov r4, r8                                                      /* r4 = r8. */\r
 251                 mov r5, r9                                                      /* r5 = r9. */\r
 252                 mov r6, r10                                                     /* r6 = r10. */\r
 253                 mov r7, r11                                                     /* r7 = r11. */\r
 254                 stmia r1!, {r4-r7}                                      /* Store the high registers that are not saved automatically. */\r
 255         #endif /* configENABLE_MPU */\r
 256 \r
 257         select_next_task:\r
 258                 cpsid i\r
 259                 bl vTaskSwitchContext\r
 260                 cpsie i\r
 261 \r
 262                 ldr r2, =pxCurrentTCB                           /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 263                 ldr r3, [r2]                                            /* Read pxCurrentTCB. */\r
 264                 ldr r1, [r3]                                            /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
 265 \r
 266         #if ( configENABLE_MPU == 1 )\r
 267                 dmb                                                                     /* Complete outstanding transfers before disabling MPU. */\r
 268                 ldr r2, =0xe000ed94                                     /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 269                 ldr r4, [r2]                                            /* Read the value of MPU_CTRL. */\r
 270                 movs r5, #1                                                     /* r5 = 1. */\r
 271                 bics r4, r5                                                     /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */\r
 272                 str r4, [r2]                                            /* Disable MPU. */\r
 273 \r
 274                 adds r3, #4                                                     /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
 275                 ldr r4, [r3]                                            /* r4 = *r3 i.e. r4 = MAIR0. */\r
 276                 ldr r2, =0xe000edc0                                     /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 277                 str r4, [r2]                                            /* Program MAIR0. */\r
 278                 ldr r2, =0xe000ed98                                     /* r2 = 0xe000ed98 [Location of RNR]. */\r
 279                 adds r3, #4                                                     /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
 280                 movs r5, #4                                                     /* r5 = 4. */\r
 281                 str  r5, [r2]                                           /* Program RNR = 4. */\r
 282                 ldmia r3!, {r6,r7}                                      /* Read first set of RBAR/RLAR from TCB. */\r
 283                 ldr  r4, =0xe000ed9c                            /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 284                 stmia r4!, {r6,r7}                                      /* Write first set of RBAR/RLAR registers. */\r
 285                 movs r5, #5                                                     /* r5 = 5. */\r
 286                 str  r5, [r2]                                           /* Program RNR = 5. */\r
 287                 ldmia r3!, {r6,r7}                                      /* Read second set of RBAR/RLAR from TCB. */\r
 288                 ldr  r4, =0xe000ed9c                            /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 289                 stmia r4!, {r6,r7}                                      /* Write second set of RBAR/RLAR registers. */\r
 290                 movs r5, #6                                                     /* r5 = 6. */\r
 291                 str  r5, [r2]                                           /* Program RNR = 6. */\r
 292                 ldmia r3!, {r6,r7}                                      /* Read third set of RBAR/RLAR from TCB. */\r
 293                 ldr  r4, =0xe000ed9c                            /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 294                 stmia r4!, {r6,r7}                                      /* Write third set of RBAR/RLAR registers. */\r
 295                 movs r5, #7                                                     /* r5 = 7. */\r
 296                 str  r5, [r2]                                           /* Program RNR = 7. */\r
 297                 ldmia r3!, {r6,r7}                                      /* Read fourth set of RBAR/RLAR from TCB. */\r
 298                 ldr  r4, =0xe000ed9c                            /* r4 = 0xe000ed9c [Location of RBAR]. */\r
 299                 stmia r4!, {r6,r7}                                      /* Write fourth set of RBAR/RLAR registers. */\r
 300 \r
 301                 ldr r2, =0xe000ed94                                     /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 302                 ldr r4, [r2]                                            /* Read the value of MPU_CTRL. */\r
 303                 movs r5, #1                                                     /* r5 = 1. */\r
 304                 orrs r4, r5                                                     /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */\r
 305                 str r4, [r2]                                            /* Enable MPU. */\r
 306                 dsb                                                                     /* Force memory writes before continuing. */\r
 307         #endif /* configENABLE_MPU */\r
 308 \r
 309         #if ( configENABLE_MPU == 1 )\r
 310                 ldmia r1!, {r0, r2-r4}                          /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
 311                 msr psplim, r2                                          /* Restore the PSPLIM register value for the task. */\r
 312                 msr control, r3                                         /* Restore the CONTROL register value for the task. */\r
 313                 mov lr, r4                                                      /* LR = r4. */\r
 314                 ldr r2, =xSecureContext                         /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 315                 str r0, [r2]                                            /* Restore the task's xSecureContext. */\r
 316                 cbz r0, restore_ns_context                      /* If there is no secure context for the task, restore the non-secure context. */\r
 317                 push {r1,r4}\r
 318                 bl SecureContext_LoadContext            /* Restore the secure context. */\r
 319                 pop {r1,r4}\r
 320                 mov lr, r4                                                      /* LR = r4. */\r
 321                 lsls r2, r4, #25                                        /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 322                 bpl restore_ns_context                          /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 323                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 324                 bx lr\r
 325         #else /* configENABLE_MPU */\r
 326                 ldmia r1!, {r0, r2-r3}                          /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
 327                 msr psplim, r2                                          /* Restore the PSPLIM register value for the task. */\r
 328                 mov lr, r3                                                      /* LR = r3. */\r
 329                 ldr r2, =xSecureContext                         /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 330                 str r0, [r2]                                            /* Restore the task's xSecureContext. */\r
 331                 cbz r0, restore_ns_context                      /* If there is no secure context for the task, restore the non-secure context. */\r
 332                 push {r1,r3}\r
 333                 bl SecureContext_LoadContext            /* Restore the secure context. */\r
 334                 pop {r1,r3}\r
 335                 mov lr, r3                                                      /* LR = r3. */\r
 336                 lsls r2, r3, #25                                        /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 337                 bpl restore_ns_context                          /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 338                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 339                 bx lr\r
 340         #endif /* configENABLE_MPU */\r
 341 \r
 342         restore_ns_context:\r
 343                 adds r1, r1, #16                                        /* Move to the high registers. */\r
 344                 ldmia r1!, {r4-r7}                                      /* Restore the high registers that are not automatically restored. */\r
 345                 mov r8, r4                                                      /* r8 = r4. */\r
 346                 mov r9, r5                                                      /* r9 = r5. */\r
 347                 mov r10, r6                                                     /* r10 = r6. */\r
 348                 mov r11, r7                                                     /* r11 = r7. */\r
 349                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 350                 subs r1, r1, #32                                        /* Go back to the low registers. */\r
 351                 ldmia r1!, {r4-r7}                                      /* Restore the low registers that are not automatically restored. */\r
 352                 bx lr\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 SVC_Handler:\r
 356         movs r0, #4\r
 357         mov r1, lr\r
 358         tst r0, r1\r
 359         beq stacking_used_msp\r
 360         mrs r0, psp\r
 361         b vPortSVCHandler_C\r
 362         stacking_used_msp:\r
 363                 mrs r0, msp\r
 364                 b vPortSVCHandler_C\r
 365 /*-----------------------------------------------------------*/\r
 366 \r
 367 vPortFreeSecureContext:\r
 368         ldr r1, [r0]                                                    /* The first item in the TCB is the top of the stack. */\r
 369         ldr r0, [r1]                                                    /* The first item on the stack is the task's xSecureContext. */\r
 370         cmp r0, #0                                                              /* Raise svc if task's xSecureContext is not NULL. */\r
 371         beq free_secure_context\r
 372         bx lr                                                                   /* There is no secure context (xSecureContext is NULL). */\r
 373         free_secure_context:\r
 374                 svc 1                                                           /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
 375                 bx lr                                                           /* Return. */\r
 376 /*-----------------------------------------------------------*/\r
 377 \r
 378         END\r