begriffs open source - freertos/blob - portable/GCC/ARM_CM23/secure/secure_context_port.c

   1 /*\r
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>\r
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   8  * this software and associated documentation files (the "Software"), to deal in\r
   9  * the Software without restriction, including without limitation the rights to\r
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
  11  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  12  * subject to the following conditions:\r
  13  *\r
  14  * The above copyright notice and this permission notice shall be included in all\r
  15  * copies or substantial portions of the Software.\r
  16  *\r
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  23  *\r
  24  * https://www.FreeRTOS.org\r
  25  * https://github.com/FreeRTOS\r
  26  *\r
  27  */\r
  28 \r
  29 /* Secure context includes. */\r
  30 #include "secure_context.h"\r
  31 \r
  32 /* Secure port macros. */\r
  33 #include "secure_port_macros.h"\r
  34 \r
  35 #if ( configENABLE_FPU == 1 )\r
  36     #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
  37 #endif\r
  38 \r
  39 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
  40 {\r
  41     /* xSecureContextHandle value is in r0. */\r
  42     __asm volatile\r
  43     (\r
  44         "       .syntax unified                                                 \n"\r
  45         "                                                                                       \n"\r
  46         "       mrs r1, ipsr                                                    \n"/* r1 = IPSR. */\r
  47         "       cbz r1, load_ctx_therad_mode                    \n"/* Do nothing if the processor is running in the Thread Mode. */\r
  48         "       ldmia r0!, {r1, r2}                                             \n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
  49         #if ( configENABLE_MPU == 1 )\r
  50             "   ldmia r1!, {r3}                                                 \n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
  51             "   msr control, r3                                                 \n"/* CONTROL = r3. */\r
  52         #endif /* configENABLE_MPU */\r
  53         "       msr psplim, r2                                                  \n"/* PSPLIM = r2. */\r
  54         "       msr psp, r1                                                             \n"/* PSP = r1. */\r
  55         "                                                                                       \n"\r
  56         " load_ctx_therad_mode:                                         \n"\r
  57         "       nop                                                                             \n"\r
  58         "                                                                                       \n"\r
  59         ::: "r0", "r1", "r2"\r
  60     );\r
  61 }\r
  62 /*-----------------------------------------------------------*/\r
  63 \r
  64 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
  65 {\r
  66     /* xSecureContextHandle value is in r0. */\r
  67     __asm volatile\r
  68     (\r
  69         "       .syntax unified                                                 \n"\r
  70         "                                                                                       \n"\r
  71         "       mrs r1, ipsr                                                    \n"/* r1 = IPSR. */\r
  72         "       cbz r1, save_ctx_therad_mode                    \n"/* Do nothing if the processor is running in the Thread Mode. */\r
  73         "       mrs r1, psp                                                             \n"/* r1 = PSP. */\r
  74         #if ( configENABLE_MPU == 1 )\r
  75             "   mrs r2, control                                                 \n"/* r2 = CONTROL. */\r
  76             "   subs r1, r1, #4                                                 \n"/* Make space for the CONTROL value on the stack. */\r
  77             "   str r1, [r0]                                                    \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
  78             "   stmia r1!, {r2}                                                 \n"/* Store CONTROL value on the stack. */\r
  79         #else /* configENABLE_MPU */\r
  80             "   str r1, [r0]                                                    \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
  81         #endif /* configENABLE_MPU */\r
  82         "       movs r1, %0                                                             \n"/* r1 = securecontextNO_STACK. */\r
  83         "       msr psplim, r1                                                  \n"/* PSPLIM = securecontextNO_STACK. */\r
  84         "       msr psp, r1                                                             \n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
  85         "                                                                                       \n"\r
  86         " save_ctx_therad_mode:                                         \n"\r
  87         "       nop                                                                             \n"\r
  88         "                                                                                       \n"\r
  89         ::"i" ( securecontextNO_STACK ) : "r1", "memory"\r
  90     );\r
  91 }\r
  92 /*-----------------------------------------------------------*/\r