begriffs open source - freertos/blob - portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>\r
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   8  * this software and associated documentation files (the "Software"), to deal in\r
   9  * the Software without restriction, including without limitation the rights to\r
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
  11  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  12  * subject to the following conditions:\r
  13  *\r
  14  * The above copyright notice and this permission notice shall be included in all\r
  15  * copies or substantial portions of the Software.\r
  16  *\r
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  23  *\r
  24  * https://www.FreeRTOS.org\r
  25  * https://github.com/FreeRTOS\r
  26  *\r
  27  */\r
  28 \r
  29 /* Standard includes. */\r
  30 #include <stdint.h>\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
  33  * is defined correctly and privileged functions are placed in correct sections. */\r
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  35 \r
  36 /* Portasm includes. */\r
  37 #include "portasm.h"\r
  38 \r
  39 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
  40  * header files. */\r
  41 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  42 \r
  43 #if ( configENABLE_FPU == 1 )\r
  44     #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.\r
  45 #endif\r
  46 \r
  47 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  48 {\r
  49     __asm volatile\r
  50     (\r
  51         "       .syntax unified                                                                 \n"\r
  52         "                                                                                                       \n"\r
  53         "       ldr  r2, pxCurrentTCBConst2                                             \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  54         "       ldr  r1, [r2]                                                                   \n"/* Read pxCurrentTCB. */\r
  55         "       ldr  r0, [r1]                                                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  56         "                                                                                                       \n"\r
  57         #if ( configENABLE_MPU == 1 )\r
  58             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
  59             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  60             "   ldr r3, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  61             "   movs r4, #1                                                                             \n"/* r4 = 1. */\r
  62             "   bics r3, r4                                                                             \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
  63             "   str r3, [r2]                                                                    \n"/* Disable MPU. */\r
  64             "                                                                                                   \n"\r
  65             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  66             "   ldr  r4, [r1]                                                                   \n"/* r4 = *r1 i.e. r4 = MAIR0. */\r
  67             "   ldr  r2, xMAIR0Const2                                                   \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  68             "   str  r4, [r2]                                                                   \n"/* Program MAIR0. */\r
  69             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
  70             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  71             "   movs r4, #4                                                                             \n"/* r4 = 4. */\r
  72             "   str  r4, [r2]                                                                   \n"/* Program RNR = 4. */\r
  73             "   ldmia r1!, {r5,r6}                                                              \n"/* Read first set of RBAR/RLAR from TCB. */\r
  74             "   ldr  r3, xRBARConst2                                                    \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
  75             "   stmia r3!, {r5,r6}                                                              \n"/* Write first set of RBAR/RLAR registers. */\r
  76             "   movs r4, #5                                                                             \n"/* r4 = 5. */\r
  77             "   str  r4, [r2]                                                                   \n"/* Program RNR = 5. */\r
  78             "   ldmia r1!, {r5,r6}                                                              \n"/* Read second set of RBAR/RLAR from TCB. */\r
  79             "   ldr  r3, xRBARConst2                                                    \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
  80             "   stmia r3!, {r5,r6}                                                              \n"/* Write second set of RBAR/RLAR registers. */\r
  81             "   movs r4, #6                                                                             \n"/* r4 = 6. */\r
  82             "   str  r4, [r2]                                                                   \n"/* Program RNR = 6. */\r
  83             "   ldmia r1!, {r5,r6}                                                              \n"/* Read third set of RBAR/RLAR from TCB. */\r
  84             "   ldr  r3, xRBARConst2                                                    \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
  85             "   stmia r3!, {r5,r6}                                                              \n"/* Write third set of RBAR/RLAR registers. */\r
  86             "   movs r4, #7                                                                             \n"/* r4 = 7. */\r
  87             "   str  r4, [r2]                                                                   \n"/* Program RNR = 7. */\r
  88             "   ldmia r1!, {r5,r6}                                                              \n"/* Read fourth set of RBAR/RLAR from TCB. */\r
  89             "   ldr  r3, xRBARConst2                                                    \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
  90             "   stmia r3!, {r5,r6}                                                              \n"/* Write fourth set of RBAR/RLAR registers. */\r
  91             "                                                                                                   \n"\r
  92             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  93             "   ldr r3, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  94             "   movs r4, #1                                                                             \n"/* r4 = 1. */\r
  95             "   orrs r3, r4                                                                             \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
  96             "   str r3, [r2]                                                                    \n"/* Enable MPU. */\r
  97             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
  98         #endif /* configENABLE_MPU */\r
  99         "                                                                                                       \n"\r
 100         #if ( configENABLE_MPU == 1 )\r
 101             "   ldm  r0!, {r1-r3}                                                               \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
 102             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
 103             "   msr  control, r2                                                                \n"/* Set this task's CONTROL value. */\r
 104             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
 105             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
 106             "   isb                                                                                             \n"\r
 107             "   bx   r3                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
 108         #else /* configENABLE_MPU */\r
 109             "   ldm  r0!, {r1-r2}                                                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 110             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
 111             "   movs r1, #2                                                                             \n"/* r1 = 2. */\r
 112             "   msr  CONTROL, r1                                                                \n"/* Switch to use PSP in the thread mode. */\r
 113             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
 114             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
 115             "   isb                                                                                             \n"\r
 116             "   bx   r2                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
 117         #endif /* configENABLE_MPU */\r
 118         "                                                                                                       \n"\r
 119         "       .align 4                                                                                \n"\r
 120         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 121         #if ( configENABLE_MPU == 1 )\r
 122             "xMPUCTRLConst2: .word 0xe000ed94                                   \n"\r
 123             "xMAIR0Const2: .word 0xe000edc0                                             \n"\r
 124             "xRNRConst2: .word 0xe000ed98                                               \n"\r
 125             "xRBARConst2: .word 0xe000ed9c                                              \n"\r
 126         #endif /* configENABLE_MPU */\r
 127     );\r
 128 }\r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 132 {\r
 133     __asm volatile\r
 134     (\r
 135         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 136         "       movs r1, #1                                                                             \n"/* r1 = 1. */\r
 137         "       tst r0, r1                                                                              \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */\r
 138         "       beq running_privileged                                                  \n"/* If the result of previous AND operation was 0, branch. */\r
 139         "       movs r0, #0                                                                             \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 140         "       bx lr                                                                                   \n"/* Return. */\r
 141         " running_privileged:                                                           \n"\r
 142         "       movs r0, #1                                                                             \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 143         "       bx lr                                                                                   \n"/* Return. */\r
 144         "                                                                                                       \n"\r
 145         "       .align 4                                                                                \n"\r
 146         ::: "r0", "r1", "memory"\r
 147     );\r
 148 }\r
 149 /*-----------------------------------------------------------*/\r
 150 \r
 151 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 152 {\r
 153     __asm volatile\r
 154     (\r
 155         "       mrs  r0, control                                                                \n"/* Read the CONTROL register. */\r
 156         "       movs r1, #1                                                                             \n"/* r1 = 1. */\r
 157         "       bics r0, r1                                                                             \n"/* Clear the bit 0. */\r
 158         "       msr  control, r0                                                                \n"/* Write back the new CONTROL value. */\r
 159         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 160         ::: "r0", "r1", "memory"\r
 161     );\r
 162 }\r
 163 /*-----------------------------------------------------------*/\r
 164 \r
 165 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 166 {\r
 167     __asm volatile\r
 168     (\r
 169         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 170         "       movs r1, #1                                                                             \n"/* r1 = 1. */\r
 171         "       orrs r0, r1                                                                             \n"/* r0 = r0 | r1. */\r
 172         "       msr control, r0                                                                 \n"/* CONTROL = r0. */\r
 173         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 174         ::: "r0", "r1", "memory"\r
 175     );\r
 176 }\r
 177 /*-----------------------------------------------------------*/\r
 178 \r
 179 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 180 {\r
 181     __asm volatile\r
 182     (\r
 183         "       ldr r0, xVTORConst                                                              \n"/* Use the NVIC offset register to locate the stack. */\r
 184         "       ldr r0, [r0]                                                                    \n"/* Read the VTOR register which gives the address of vector table. */\r
 185         "       ldr r0, [r0]                                                                    \n"/* The first entry in vector table is stack pointer. */\r
 186         "       msr msp, r0                                                                             \n"/* Set the MSP back to the start of the stack. */\r
 187         "       cpsie i                                                                                 \n"/* Globally enable interrupts. */\r
 188         "       dsb                                                                                             \n"\r
 189         "       isb                                                                                             \n"\r
 190         "       svc %0                                                                                  \n"/* System call to start the first task. */\r
 191         "       nop                                                                                             \n"\r
 192         "                                                                                                       \n"\r
 193         "   .align 4                                                                            \n"\r
 194         "xVTORConst: .word 0xe000ed08                                           \n"\r
 195         ::"i" ( portSVC_START_SCHEDULER ) : "memory"\r
 196     );\r
 197 }\r
 198 /*-----------------------------------------------------------*/\r
 199 \r
 200 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 201 {\r
 202     __asm volatile\r
 203     (\r
 204         "       mrs r0, PRIMASK                                                                 \n"\r
 205         "       cpsid i                                                                                 \n"\r
 206         "       bx lr                                                                                   \n"\r
 207         ::: "memory"\r
 208     );\r
 209 }\r
 210 /*-----------------------------------------------------------*/\r
 211 \r
 212 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 213 {\r
 214     __asm volatile\r
 215     (\r
 216         "       msr PRIMASK, r0                                                                 \n"\r
 217         "       bx lr                                                                                   \n"\r
 218         ::: "memory"\r
 219     );\r
 220 }\r
 221 /*-----------------------------------------------------------*/\r
 222 \r
 223 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 224 {\r
 225     __asm volatile\r
 226     (\r
 227         "       .syntax unified                                                                 \n"\r
 228         "                                                                                                       \n"\r
 229         "       mrs r0, psp                                                                             \n"/* Read PSP in r0. */\r
 230         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 231         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 232         #if ( configENABLE_MPU == 1 )\r
 233             "   subs r0, r0, #44                                                                \n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
 234             "   str r0, [r1]                                                                    \n"/* Save the new top of stack in TCB. */\r
 235             "   mrs r1, psplim                                                                  \n"/* r1 = PSPLIM. */\r
 236             "   mrs r2, control                                                                 \n"/* r2 = CONTROL. */\r
 237             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 238             "   stmia r0!, {r1-r7}                                                              \n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */\r
 239             "   mov r4, r8                                                                              \n"/* r4 = r8. */\r
 240             "   mov r5, r9                                                                              \n"/* r5 = r9. */\r
 241             "   mov r6, r10                                                                             \n"/* r6 = r10. */\r
 242             "   mov r7, r11                                                                             \n"/* r7 = r11. */\r
 243             "   stmia r0!, {r4-r7}                                                              \n"/* Store the high registers that are not saved automatically. */\r
 244         #else /* configENABLE_MPU */\r
 245             "   subs r0, r0, #40                                                                \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */\r
 246             "   str r0, [r1]                                                                    \n"/* Save the new top of stack in TCB. */\r
 247             "   mrs r2, psplim                                                                  \n"/* r2 = PSPLIM. */\r
 248             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 249             "   stmia r0!, {r2-r7}                                                              \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */\r
 250             "   mov r4, r8                                                                              \n"/* r4 = r8. */\r
 251             "   mov r5, r9                                                                              \n"/* r5 = r9. */\r
 252             "   mov r6, r10                                                                             \n"/* r6 = r10. */\r
 253             "   mov r7, r11                                                                             \n"/* r7 = r11. */\r
 254             "   stmia r0!, {r4-r7}                                                              \n"/* Store the high registers that are not saved automatically. */\r
 255         #endif /* configENABLE_MPU */\r
 256         "                                                                                                       \n"\r
 257         "       cpsid i                                                                                 \n"\r
 258         "       bl vTaskSwitchContext                                                   \n"\r
 259         "       cpsie i                                                                                 \n"\r
 260         "                                                                                                       \n"\r
 261         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 262         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 263         "       ldr r0, [r1]                                                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 264         "                                                                                                       \n"\r
 265         #if ( configENABLE_MPU == 1 )\r
 266             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
 267             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 268             "   ldr r3, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 269             "   movs r4, #1                                                                             \n"/* r4 = 1. */\r
 270             "   bics r3, r4                                                                             \n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */\r
 271             "   str r3, [r2]                                                                    \n"/* Disable MPU. */\r
 272             "                                                                                                   \n"\r
 273             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 274             "   ldr  r4, [r1]                                                                   \n"/* r4 = *r1 i.e. r4 = MAIR0. */\r
 275             "   ldr  r2, xMAIR0Const                                                    \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 276             "   str  r4, [r2]                                                                   \n"/* Program MAIR0. */\r
 277             "   ldr  r2, xRNRConst                                                              \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
 278             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 279             "   movs r4, #4                                                                             \n"/* r4 = 4. */\r
 280             "   str  r4, [r2]                                                                   \n"/* Program RNR = 4. */\r
 281             "   ldmia r1!, {r5,r6}                                                              \n"/* Read first set of RBAR/RLAR from TCB. */\r
 282             "   ldr  r3, xRBARConst                                                             \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
 283             "   stmia r3!, {r5,r6}                                                              \n"/* Write first set of RBAR/RLAR registers. */\r
 284             "   movs r4, #5                                                                             \n"/* r4 = 5. */\r
 285             "   str  r4, [r2]                                                                   \n"/* Program RNR = 5. */\r
 286             "   ldmia r1!, {r5,r6}                                                              \n"/* Read second set of RBAR/RLAR from TCB. */\r
 287             "   ldr  r3, xRBARConst                                                             \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
 288             "   stmia r3!, {r5,r6}                                                              \n"/* Write second set of RBAR/RLAR registers. */\r
 289             "   movs r4, #6                                                                             \n"/* r4 = 6. */\r
 290             "   str  r4, [r2]                                                                   \n"/* Program RNR = 6. */\r
 291             "   ldmia r1!, {r5,r6}                                                              \n"/* Read third set of RBAR/RLAR from TCB. */\r
 292             "   ldr  r3, xRBARConst                                                             \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
 293             "   stmia r3!, {r5,r6}                                                              \n"/* Write third set of RBAR/RLAR registers. */\r
 294             "   movs r4, #7                                                                             \n"/* r4 = 7. */\r
 295             "   str  r4, [r2]                                                                   \n"/* Program RNR = 7. */\r
 296             "   ldmia r1!, {r5,r6}                                                              \n"/* Read fourth set of RBAR/RLAR from TCB. */\r
 297             "   ldr  r3, xRBARConst                                                             \n"/* r3 = 0xe000ed9c [Location of RBAR]. */\r
 298             "   stmia r3!, {r5,r6}                                                              \n"/* Write fourth set of RBAR/RLAR registers. */\r
 299             "                                                                                                   \n"\r
 300             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 301             "   ldr r3, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 302             "   movs r4, #1                                                                             \n"/* r4 = 1. */\r
 303             "   orrs r3, r4                                                                             \n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */\r
 304             "   str r3, [r2]                                                                    \n"/* Enable MPU. */\r
 305             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
 306         #endif /* configENABLE_MPU */\r
 307         "                                                                                                       \n"\r
 308         #if ( configENABLE_MPU == 1 )\r
 309             "   adds r0, r0, #28                                                                \n"/* Move to the high registers. */\r
 310             "   ldmia r0!, {r4-r7}                                                              \n"/* Restore the high registers that are not automatically restored. */\r
 311             "   mov r8, r4                                                                              \n"/* r8 = r4. */\r
 312             "   mov r9, r5                                                                              \n"/* r9 = r5. */\r
 313             "   mov r10, r6                                                                             \n"/* r10 = r6. */\r
 314             "   mov r11, r7                                                                             \n"/* r11 = r7. */\r
 315             "   msr psp, r0                                                                             \n"/* Remember the new top of stack for the task. */\r
 316             "   subs r0, r0, #44                                                                \n"/* Move to the starting of the saved context. */\r
 317             "   ldmia r0!, {r1-r7}                                                              \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */\r
 318             "   msr psplim, r1                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 319             "   msr control, r2                                                                 \n"/* Restore the CONTROL register value for the task. */\r
 320             "   bx r3                                                                                   \n"\r
 321         #else /* configENABLE_MPU */\r
 322             "   adds r0, r0, #24                                                                \n"/* Move to the high registers. */\r
 323             "   ldmia r0!, {r4-r7}                                                              \n"/* Restore the high registers that are not automatically restored. */\r
 324             "   mov r8, r4                                                                              \n"/* r8 = r4. */\r
 325             "   mov r9, r5                                                                              \n"/* r9 = r5. */\r
 326             "   mov r10, r6                                                                             \n"/* r10 = r6. */\r
 327             "   mov r11, r7                                                                             \n"/* r11 = r7. */\r
 328             "   msr psp, r0                                                                             \n"/* Remember the new top of stack for the task. */\r
 329             "   subs r0, r0, #40                                                                \n"/* Move to the starting of the saved context. */\r
 330             "   ldmia r0!, {r2-r7}                                                              \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */\r
 331             "   msr psplim, r2                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 332             "   bx r3                                                                                   \n"\r
 333         #endif /* configENABLE_MPU */\r
 334         "                                                                                                       \n"\r
 335         "       .align 4                                                                                \n"\r
 336         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 337         #if ( configENABLE_MPU == 1 )\r
 338             "xMPUCTRLConst: .word 0xe000ed94                                    \n"\r
 339             "xMAIR0Const: .word 0xe000edc0                                              \n"\r
 340             "xRNRConst: .word 0xe000ed98                                                \n"\r
 341             "xRBARConst: .word 0xe000ed9c                                               \n"\r
 342         #endif /* configENABLE_MPU */\r
 343     );\r
 344 }\r
 345 /*-----------------------------------------------------------*/\r
 346 \r
 347 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 348 {\r
 349     __asm volatile\r
 350     (\r
 351         "       movs r0, #4                                                                             \n"\r
 352         "       mov r1, lr                                                                              \n"\r
 353         "       tst r0, r1                                                                              \n"\r
 354         "       beq stacking_used_msp                                                   \n"\r
 355         "       mrs r0, psp                                                                             \n"\r
 356         "       ldr r2, svchandler_address_const                                \n"\r
 357         "       bx r2                                                                                   \n"\r
 358         " stacking_used_msp:                                                            \n"\r
 359         "       mrs r0, msp                                                                             \n"\r
 360         "       ldr r2, svchandler_address_const                                \n"\r
 361         "       bx r2                                                                                   \n"\r
 362         "                                                                                                       \n"\r
 363         "       .align 4                                                                                \n"\r
 364         "svchandler_address_const: .word vPortSVCHandler_C      \n"\r
 365     );\r
 366 }\r
 367 /*-----------------------------------------------------------*/\r