2 * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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5 * SPDX-License-Identifier: MIT
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33 #include <avr/interrupt.h>
39 /*-----------------------------------------------------------
40 * Implementation of functions defined in portable.h for the AVR port.
41 *----------------------------------------------------------*/
43 /* Start tasks with interrupts enabled. */
44 #define portFLAGS_INT_ENABLED ( (StackType_t) 0x80 )
46 #if defined( portUSE_WDTO)
47 #warning "Watchdog Timer used for scheduler."
48 #define portSCHEDULER_ISR WDT_vect
50 #elif defined( portUSE_TIMER0 )
51 /* Hardware constants for Timer0. */
52 #warning "Timer0 used for scheduler."
53 #define portSCHEDULER_ISR TIMER0_COMPA_vect
54 #define portCLEAR_COUNTER_ON_MATCH ( (uint8_t) _BV(WGM01) )
55 #define portPRESCALE_1024 ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
56 #define portCLOCK_PRESCALER ( (uint32_t) 1024 )
57 #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( (uint8_t) _BV(OCIE0A) )
58 #define portOCRL OCR0A
59 #define portTCCRa TCCR0A
60 #define portTCCRb TCCR0B
61 #define portTIMSK TIMSK0
62 #define portTIFR TIFR0
66 /*-----------------------------------------------------------*/
68 /* We require the address of the pxCurrentTCB variable, but don't want to know
69 any details of its type. */
71 extern volatile TCB_t * volatile pxCurrentTCB;
73 /*-----------------------------------------------------------*/
76 Enable the watchdog timer, configuring it for expire after
77 (value) timeout (which is a combination of the WDP0
80 This function is derived from <avr/wdt.h> but enables only
81 the interrupt bit (WDIE), rather than the reset bit (WDE).
83 Can't find it documented but the WDT, once enabled,
84 rolls over and fires a new interrupt each time.
86 See also the symbolic constants WDTO_15MS et al.
88 Updated to match avr-libc 2.0.0
91 #if defined( portUSE_WDTO)
94 __attribute__ ((__always_inline__))
95 void wdt_interrupt_enable (const uint8_t value)
97 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
99 __asm__ __volatile__ (
100 "in __tmp_reg__,__SREG__" "\n\t"
104 "out __SREG__,__tmp_reg__" "\n\t"
107 : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
108 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
109 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
110 _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
116 __asm__ __volatile__ (
117 "in __tmp_reg__,__SREG__" "\n\t"
121 "out __SREG__,__tmp_reg__" "\n\t"
124 : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
125 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
126 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
127 _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
134 /*-----------------------------------------------------------*/
136 Enable the watchdog timer, configuring it for expire after
137 (value) timeout (which is a combination of the WDP0
140 This function is derived from <avr/wdt.h> but enables both
141 the reset bit (WDE), and the interrupt bit (WDIE).
143 This will ensure that if the interrupt is not serviced
144 before the second timeout, the AVR will reset.
146 Servicing the interrupt automatically clears it,
147 and ensures the AVR does not reset.
149 Can't find it documented but the WDT, once enabled,
150 rolls over and fires a new interrupt each time.
152 See also the symbolic constants WDTO_15MS et al.
154 Updated to match avr-libc 2.0.0
157 #if defined( portUSE_WDTO)
160 __attribute__ ((__always_inline__))
161 void wdt_interrupt_reset_enable (const uint8_t value)
163 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
165 __asm__ __volatile__ (
166 "in __tmp_reg__,__SREG__" "\n\t"
170 "out __SREG__,__tmp_reg__" "\n\t"
173 : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
174 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
175 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
176 _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
182 __asm__ __volatile__ (
183 "in __tmp_reg__,__SREG__" "\n\t"
187 "out __SREG__,__tmp_reg__" "\n\t"
190 : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
191 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
192 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
193 _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
200 /*-----------------------------------------------------------*/
203 * Macro to save all the general purpose registers, the save the stack pointer
206 * The first thing we do is save the flags then disable interrupts. This is to
207 * guard our stack against having a context switch interrupt after we have already
208 * pushed the registers onto the stack - causing the 32 registers to be on the
211 * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however
212 * some of the math routines make use of R1.
214 * r0 is set to __tmp_reg__ as the compiler expects it to be thus.
216 * #if defined(__AVR_HAVE_RAMPZ__)
217 * #define __RAMPZ__ 0x3B
220 * #if defined(__AVR_3_BYTE_PC__)
221 * #define __EIND__ 0x3C
224 * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
225 * so we need not worry about reading/writing to the stack pointer.
227 #if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
228 /* 3-Byte PC Save with RAMPZ */
229 #define portSAVE_CONTEXT() \
230 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
231 "in __tmp_reg__, __SREG__ \n\t" \
233 "push __tmp_reg__ \n\t" \
234 "in __tmp_reg__, 0x3B \n\t" \
235 "push __tmp_reg__ \n\t" \
236 "in __tmp_reg__, 0x3C \n\t" \
237 "push __tmp_reg__ \n\t" \
238 "push __zero_reg__ \n\t" \
239 "clr __zero_reg__ \n\t" \
270 "lds r26, pxCurrentTCB \n\t" \
271 "lds r27, pxCurrentTCB + 1 \n\t" \
272 "in __tmp_reg__, __SP_L__ \n\t" \
273 "st x+, __tmp_reg__ \n\t" \
274 "in __tmp_reg__, __SP_H__ \n\t" \
275 "st x+, __tmp_reg__ \n\t" \
277 #elif defined(__AVR_HAVE_RAMPZ__)
278 /* 2-Byte PC Save with RAMPZ */
279 #define portSAVE_CONTEXT() \
280 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
281 "in __tmp_reg__, __SREG__ \n\t" \
283 "push __tmp_reg__ \n\t" \
284 "in __tmp_reg__, 0x3B \n\t" \
285 "push __tmp_reg__ \n\t" \
286 "push __zero_reg__ \n\t" \
287 "clr __zero_reg__ \n\t" \
318 "lds r26, pxCurrentTCB \n\t" \
319 "lds r27, pxCurrentTCB + 1 \n\t" \
320 "in __tmp_reg__, __SP_L__ \n\t" \
321 "st x+, __tmp_reg__ \n\t" \
322 "in __tmp_reg__, __SP_H__ \n\t" \
323 "st x+, __tmp_reg__ \n\t" \
327 #define portSAVE_CONTEXT() \
328 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
329 "in __tmp_reg__, __SREG__ \n\t" \
331 "push __tmp_reg__ \n\t" \
332 "push __zero_reg__ \n\t" \
333 "clr __zero_reg__ \n\t" \
364 "lds r26, pxCurrentTCB \n\t" \
365 "lds r27, pxCurrentTCB + 1 \n\t" \
366 "in __tmp_reg__, __SP_L__ \n\t" \
367 "st x+, __tmp_reg__ \n\t" \
368 "in __tmp_reg__, __SP_H__ \n\t" \
369 "st x+, __tmp_reg__ \n\t" \
374 * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
375 * the context save so we can write to the stack pointer.
377 #if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
378 /* 3-Byte PC Restore with RAMPZ */
379 #define portRESTORE_CONTEXT() \
380 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
381 "lds r27, pxCurrentTCB + 1 \n\t" \
383 "out __SP_L__, r28 \n\t" \
385 "out __SP_H__, r29 \n\t" \
416 "pop __zero_reg__ \n\t" \
417 "pop __tmp_reg__ \n\t" \
418 "out 0x3C, __tmp_reg__ \n\t" \
419 "pop __tmp_reg__ \n\t" \
420 "out 0x3B, __tmp_reg__ \n\t" \
421 "pop __tmp_reg__ \n\t" \
422 "out __SREG__, __tmp_reg__ \n\t" \
423 "pop __tmp_reg__ \n\t" \
425 #elif defined(__AVR_HAVE_RAMPZ__)
426 /* 2-Byte PC Restore with RAMPZ */
427 #define portRESTORE_CONTEXT() \
428 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
429 "lds r27, pxCurrentTCB + 1 \n\t" \
431 "out __SP_L__, r28 \n\t" \
433 "out __SP_H__, r29 \n\t" \
464 "pop __zero_reg__ \n\t" \
465 "pop __tmp_reg__ \n\t" \
466 "out 0x3B, __tmp_reg__ \n\t" \
467 "pop __tmp_reg__ \n\t" \
468 "out __SREG__, __tmp_reg__ \n\t" \
469 "pop __tmp_reg__ \n\t" \
472 /* 2-Byte PC Restore */
473 #define portRESTORE_CONTEXT() \
474 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
475 "lds r27, pxCurrentTCB + 1 \n\t" \
477 "out __SP_L__, r28 \n\t" \
479 "out __SP_H__, r29 \n\t" \
510 "pop __zero_reg__ \n\t" \
511 "pop __tmp_reg__ \n\t" \
512 "out __SREG__, __tmp_reg__ \n\t" \
513 "pop __tmp_reg__ \n\t" \
516 /*-----------------------------------------------------------*/
519 * Perform hardware setup to enable ticks from relevant Timer.
521 static void prvSetupTimerInterrupt( void );
522 /*-----------------------------------------------------------*/
525 * See header file for description.
527 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
530 /* Simulate how the stack would look after a call to vPortYield() generated by
533 /* The start of the task code will be popped off the stack last, so place
535 usAddress = ( uint16_t ) pxCode;
536 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
540 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
543 #if defined(__AVR_3_BYTE_PC__)
544 /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
545 * program counter. When a code address is stored on the stack, it takes 3 bytes
546 * instead of 2 for the other ATmega* chips.
548 * Store 0 as the top byte since we force all task routines to the bottom 128K
549 * of flash. We do this by using the .lowtext label in the linker script.
551 * In order to do this properly, we would need to get a full 3-byte pointer to
552 * pxCode. That requires a change to GCC. Not likely to happen any time soon.
558 /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
559 portSAVE_CONTEXT places the flags on the stack immediately after r0
560 to ensure the interrupts get disabled as soon as possible, and so ensuring
561 the stack use is minimal should a context switch interrupt occur. */
562 *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
564 *pxTopOfStack = portFLAGS_INT_ENABLED;
567 #if defined(__AVR_3_BYTE_PC__)
568 /* If we have an ATmega256x, we are also saving the EIND register.
569 * We should default to 0.
571 *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
575 #if defined(__AVR_HAVE_RAMPZ__)
576 /* We are saving the RAMPZ register.
577 * We should default to 0.
579 *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
583 /* Now the remaining registers. The compiler expects R1 to be 0. */
584 *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
586 /* Leave R2 - R23 untouched */
589 /* Place the parameter on the stack in the expected location. */
590 usAddress = ( uint16_t ) pvParameters;
591 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
595 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
597 /* Leave register R26 - R31 untouched */
602 /*-----------------------------------------------------------*/
604 BaseType_t xPortStartScheduler( void )
606 /* Setup the relevant timer hardware to generate the tick. */
607 prvSetupTimerInterrupt();
609 /* Restore the context of the first task that is going to run. */
610 portRESTORE_CONTEXT();
612 /* Simulate a function call end as generated by the compiler. We will now
613 jump to the start of the task the context of which we have just restored. */
614 __asm__ __volatile__ ( "ret" );
616 /* Should not get here. */
619 /*-----------------------------------------------------------*/
621 void vPortEndScheduler( void )
623 /* It is unlikely that the ATmega port will get stopped. */
625 /*-----------------------------------------------------------*/
628 * Manual context switch. The first thing we do is save the registers so we
629 * can use a naked attribute.
631 void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
632 void vPortYield( void )
635 vTaskSwitchContext();
636 portRESTORE_CONTEXT();
638 __asm__ __volatile__ ( "ret" );
640 /*-----------------------------------------------------------*/
643 * Manual context switch callable from ISRs. The first thing we do is save
644 * the registers so we can use a naked attribute.
646 void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
647 void vPortYieldFromISR(void)
650 vTaskSwitchContext();
651 portRESTORE_CONTEXT();
653 __asm__ __volatile__ ( "reti" );
655 /*-----------------------------------------------------------*/
658 * Context switch function used by the tick. This must be identical to
659 * vPortYield() from the call to vTaskSwitchContext() onwards. The only
660 * difference from vPortYield() is the tick count is incremented as the
661 * call comes from the tick ISR.
663 void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
664 void vPortYieldFromTick( void )
667 if( xTaskIncrementTick() != pdFALSE )
669 vTaskSwitchContext();
671 portRESTORE_CONTEXT();
673 __asm__ __volatile__ ( "ret" );
675 /*-----------------------------------------------------------*/
677 #if defined(portUSE_WDTO)
679 * Setup WDT to generate a tick interrupt.
681 void prvSetupTimerInterrupt( void )
686 /* set up WDT Interrupt (rather than the WDT Reset). */
687 wdt_interrupt_enable( portUSE_WDTO );
690 #elif defined (portUSE_TIMER0)
692 * Setup Timer0 compare match A to generate a tick interrupt.
694 static void prvSetupTimerInterrupt( void )
696 uint32_t ulCompareMatch;
699 /* Using 8bit Timer0 to generate the tick. Correct fuses must be
700 selected for the configCPU_CLOCK_HZ clock.*/
702 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
704 /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
705 ulCompareMatch /= portCLOCK_PRESCALER;
707 /* Adjust for correct value. */
708 ulCompareMatch -= ( uint32_t ) 1;
710 /* Setup compare match value for compare match A. Interrupts are disabled
711 before this is called so we need not worry here. */
712 ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
713 portOCRL = ucLowByte;
715 /* Setup clock source and compare match behaviour. */
716 portTCCRa = portCLEAR_COUNTER_ON_MATCH;
717 portTCCRb = portPRESCALE_1024;
720 /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
721 ucLowByte = portTIMSK;
722 ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
723 portTIMSK = ucLowByte;
728 /*-----------------------------------------------------------*/
730 #if configUSE_PREEMPTION == 1
733 * Tick ISR for preemptive scheduler. We can use a naked attribute as
734 * the context is saved at the start of vPortYieldFromTick(). The tick
735 * count is incremented after the context is saved.
737 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
740 ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
741 /* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
743 ISR(portSCHEDULER_ISR)
745 vPortYieldFromTick();
746 __asm__ __volatile__ ( "reti" );
751 * Tick ISR for the cooperative scheduler. All this does is increment the
752 * tick count. We don't need to switch context, this can only be done by
753 * manual calls to taskYIELD();
755 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
757 ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
758 /* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
760 ISR(portSCHEDULER_ISR)
762 xTaskIncrementTick();