1 /*******************************************************************************
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2 * © 2013 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 ********************************************************************************
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21 Version Control Information (Perforce)
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22 $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/MEC1322.h $
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23 ********************************************************************************
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25 $DateTime: 2015/12/23 15:37:58 $
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26 $Author: akrishnan $
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27 Change Description: Initial revision for MEC1322
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28 ******************************************************************************/
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29 /** @file smscmmcr.h
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30 * brief the mmcr definitions
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32 ******************************************************************************/
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36 //NOTE: Please Don't edit this File, this is extrated from the Spread sheet
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37 // : //depotAE/projects/MEC1322/docs/MMCRs/MEC1322_FPGA1_Query_All_Addressing_ResultSet.csv
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38 typedef volatile unsigned char VUINT8;
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39 typedef volatile unsigned short int VUINT16;
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40 typedef volatile unsigned long int VUINT32;
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42 /***************************************************************
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44 ***************************************************************/
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45 #define ADDR_PWM_0_COUNTER_ON_TIME 0x40005800
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46 #define MMCR_PWM_0_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_ON_TIME))
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48 #define ADDR_PWM_0_COUNTER_OFF_TIME 0x40005804
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49 #define MMCR_PWM_0_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_0_COUNTER_OFF_TIME))
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51 #define ADDR_PWM_0_CONFIGURATION 0x40005808
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52 #define MMCR_PWM_0_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_0_CONFIGURATION))
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54 #define ADDR_PWM_1_COUNTER_ON_TIME 0x40005810
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55 #define MMCR_PWM_1_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_ON_TIME))
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57 #define ADDR_PWM_1_COUNTER_OFF_TIME 0x40005814
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58 #define MMCR_PWM_1_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_1_COUNTER_OFF_TIME))
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60 #define ADDR_PWM_1_CONFIGURATION 0x40005818
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61 #define MMCR_PWM_1_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_1_CONFIGURATION))
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63 #define ADDR_PWM_2_COUNTER_ON_TIME 0x40005820
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64 #define MMCR_PWM_2_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_ON_TIME))
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66 #define ADDR_PWM_2_COUNTER_OFF_TIME 0x40005824
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67 #define MMCR_PWM_2_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_2_COUNTER_OFF_TIME))
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69 #define ADDR_PWM_2_CONFIGURATION 0x40005828
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70 #define MMCR_PWM_2_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_2_CONFIGURATION))
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72 #define ADDR_PWM_3_COUNTER_ON_TIME 0x40005830
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73 #define MMCR_PWM_3_COUNTER_ON_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_ON_TIME))
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75 #define ADDR_PWM_3_COUNTER_OFF_TIME 0x40005834
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76 #define MMCR_PWM_3_COUNTER_OFF_TIME (*(VUINT32 *)(ADDR_PWM_3_COUNTER_OFF_TIME))
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78 #define ADDR_PWM_3_CONFIGURATION 0x40005838
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79 #define MMCR_PWM_3_CONFIGURATION (*(VUINT32 *)(ADDR_PWM_3_CONFIGURATION))
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81 /***************************************************************
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83 ***************************************************************/
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84 #define ADDR_PECI_WRITE_DATA 0x40006400
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85 #define MMCR_PECI_WRITE_DATA (*(VUINT32 *)(ADDR_PECI_WRITE_DATA))
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87 #define ADDR_PECI_READ_DATA 0x40006404
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88 #define MMCR_PECI_READ_DATA (*(VUINT32 *)(ADDR_PECI_READ_DATA))
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90 #define ADDR_PECI_CONTROL 0x40006408
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91 #define MMCR_PECI_CONTROL (*(VUINT32 *)(ADDR_PECI_CONTROL))
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93 #define ADDR_PECI_STATUS_1 0x4000640C
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94 #define MMCR_PECI_STATUS_1 (*(VUINT32 *)(ADDR_PECI_STATUS_1))
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96 #define ADDR_PECI_STATUS_2 0x40006410
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97 #define MMCR_PECI_STATUS_2 (*(VUINT32 *)(ADDR_PECI_STATUS_2))
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99 #define ADDR_PECI_ERROR 0x40006414
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100 #define MMCR_PECI_ERROR (*(VUINT32 *)(ADDR_PECI_ERROR))
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102 #define ADDR_PECI_INTERRUPT_ENABLE_1 0x40006418
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103 #define MMCR_PECI_INTERRUPT_ENABLE_1 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_1))
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105 #define ADDR_PECI_INTERRUPT_ENABLE_2 0x4000641C
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106 #define MMCR_PECI_INTERRUPT_ENABLE_2 (*(VUINT32 *)(ADDR_PECI_INTERRUPT_ENABLE_2))
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108 #define ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE 0x40006420
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109 #define MMCR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_LOW_BYTE))
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111 #define ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE 0x40006424
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112 #define MMCR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_OPTIMAL_BIT_TIME_HIGH_BYTE))
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114 #define ADDR_PECI_REQUEST_TIMER_LOW_BYTE 0x40006428
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115 #define MMCR_PECI_REQUEST_TIMER_LOW_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_LOW_BYTE))
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117 #define ADDR_PECI_REQUEST_TIMER_HIGH_BYTE 0x4000642C
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118 #define MMCR_PECI_REQUEST_TIMER_HIGH_BYTE (*(VUINT32 *)(ADDR_PECI_REQUEST_TIMER_HIGH_BYTE))
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120 #define ADDR_PECI_BLOCK_ID 0x40006440
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121 #define MMCR_PECI_BLOCK_ID (*(VUINT32 *)(ADDR_PECI_BLOCK_ID))
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123 #define ADDR_PECI_BLOCK_REVISION 0x40006444
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124 #define MMCR_PECI_BLOCK_REVISION (*(VUINT32 *)(ADDR_PECI_BLOCK_REVISION))
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126 /***************************************************************
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127 * ACPI EC Interface
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128 ***************************************************************/
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129 #define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0 0x400F0D00
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130 #define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_0))
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132 #define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1 0x400F0D01
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133 #define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_1))
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135 #define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2 0x400F0D02
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136 #define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_2))
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138 #define ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3 0x400F0D03
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139 #define MMCR_ACPI_0_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_EC2OS_DATA_EC_BYTE_3))
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141 #define ADDR_ACPI_0_STATUS_EC 0x400F0D04
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142 #define MMCR_ACPI_0_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_0_STATUS_EC))
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144 #define ADDR_ACPI_0_BYTE_CONTROL_EC 0x400F0D05
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145 #define MMCR_ACPI_0_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_0_BYTE_CONTROL_EC))
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147 #define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08
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148 #define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))
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150 #define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0 0x400F0D08
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151 #define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_0))
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153 #define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1 0x400F0D09
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154 #define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_1))
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156 #define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2 0x400F0D0A
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157 #define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_2))
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159 #define ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3 0x400F0D0B
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160 #define MMCR_ACPI_0_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_0_OS2EC_DATA_EC_BYTE_3))
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162 #define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0 0x400F1100
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163 #define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_0))
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165 #define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1 0x400F1101
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166 #define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_1))
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168 #define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2 0x400F1102
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169 #define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_2))
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171 #define ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3 0x400F1103
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172 #define MMCR_ACPI_1_EC2OS_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_EC2OS_DATA_EC_BYTE_3))
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174 #define ADDR_ACPI_1_STATUS_EC 0x400F1104
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175 #define MMCR_ACPI_1_STATUS_EC (*(VUINT8 *)(ADDR_ACPI_1_STATUS_EC))
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177 #define ADDR_ACPI_1_BYTE_CONTROL_EC 0x400F1105
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178 #define MMCR_ACPI_1_BYTE_CONTROL_EC (*(VUINT8 *)(ADDR_ACPI_1_BYTE_CONTROL_EC))
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180 #define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108
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181 #define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))
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183 #define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0 0x400F1108
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184 #define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_0 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_0))
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186 #define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1 0x400F1109
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187 #define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_1 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_1))
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189 #define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2 0x400F110A
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190 #define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_2 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_2))
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192 #define ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3 0x400F110B
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193 #define MMCR_ACPI_1_OS2EC_DATA_EC_BYTE_3 (*(VUINT8 *)(ADDR_ACPI_1_OS2EC_DATA_EC_BYTE_3))
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195 /***************************************************************
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196 * Keyboard Matrix Scan Support
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197 ***************************************************************/
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198 #define ADDR_KEYBOARD_KSO_SELECT 0x40009C04
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199 #define MMCR_KEYBOARD_KSO_SELECT (*(VUINT32 *)(ADDR_KEYBOARD_KSO_SELECT))
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201 #define ADDR_KEYBOARD_KSI_INPUT 0x40009C08
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202 #define MMCR_KEYBOARD_KSI_INPUT (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INPUT))
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204 #define ADDR_KEYBOARD_KSI_STATUS 0x40009C0C
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205 #define MMCR_KEYBOARD_KSI_STATUS (*(VUINT32 *)(ADDR_KEYBOARD_KSI_STATUS))
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207 #define ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE 0x40009C10
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208 #define MMCR_KEYBOARD_KSI_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_KEYBOARD_KSI_INTERRUPT_ENABLE))
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210 #define ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL 0x40009C14
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211 #define MMCR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL (*(VUINT32 *)(ADDR_KEYBOARD_KEYSCAN_EXTENDED_CONTROL))
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213 /***************************************************************
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214 * PS/2 Device Interface
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215 ***************************************************************/
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216 #define ADDR_PS2_3_STATUS 0x400090C8
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217 #define MMCR_PS2_3_STATUS (*(VUINT8 *)(ADDR_PS2_3_STATUS))
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219 #define ADDR_PS2_3_CONTROL 0x400090C4
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220 #define MMCR_PS2_3_CONTROL (*(VUINT8 *)(ADDR_PS2_3_CONTROL))
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222 #define ADDR_PS2_3_RECEIVE_BUFFER 0x400090C0
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223 #define MMCR_PS2_3_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_3_RECEIVE_BUFFER))
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225 #define ADDR_PS2_3_TRANSMIT_BUFFER 0x400090C0
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226 #define MMCR_PS2_3_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_3_TRANSMIT_BUFFER))
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228 #define ADDR_PS2_0_TRANSMIT_BUFFER 0x40009000
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229 #define MMCR_PS2_0_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_0_TRANSMIT_BUFFER))
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231 #define ADDR_PS2_0_RECEIVE_BUFFER 0x40009000
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232 #define MMCR_PS2_0_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_0_RECEIVE_BUFFER))
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234 #define ADDR_PS2_0_CONTROL 0x40009004
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235 #define MMCR_PS2_0_CONTROL (*(VUINT8 *)(ADDR_PS2_0_CONTROL))
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237 #define ADDR_PS2_0_STATUS 0x40009008
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238 #define MMCR_PS2_0_STATUS (*(VUINT8 *)(ADDR_PS2_0_STATUS))
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240 #define ADDR_PS2_1_TRANSMIT_BUFFER 0x40009040
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241 #define MMCR_PS2_1_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_1_TRANSMIT_BUFFER))
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243 #define ADDR_PS2_1_RECEIVE_BUFFER 0x40009040
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244 #define MMCR_PS2_1_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_1_RECEIVE_BUFFER))
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246 #define ADDR_PS2_1_CONTROL 0x40009044
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247 #define MMCR_PS2_1_CONTROL (*(VUINT8 *)(ADDR_PS2_1_CONTROL))
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249 #define ADDR_PS2_1_STATUS 0x40009048
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250 #define MMCR_PS2_1_STATUS (*(VUINT8 *)(ADDR_PS2_1_STATUS))
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252 #define ADDR_PS2_2_RECEIVE_BUFFER 0x40009080
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253 #define MMCR_PS2_2_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_PS2_2_RECEIVE_BUFFER))
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255 #define ADDR_PS2_2_TRANSMIT_BUFFER 0x40009080
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256 #define MMCR_PS2_2_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_PS2_2_TRANSMIT_BUFFER))
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258 #define ADDR_PS2_2_CONTROL 0x40009084
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259 #define MMCR_PS2_2_CONTROL (*(VUINT8 *)(ADDR_PS2_2_CONTROL))
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261 #define ADDR_PS2_2_STATUS 0x40009088
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262 #define MMCR_PS2_2_STATUS (*(VUINT8 *)(ADDR_PS2_2_STATUS))
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264 /***************************************************************
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265 * 8042 Host Interface
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266 ***************************************************************/
\r
267 #define ADDR_8042_ACTIVATE 0x400F0730
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268 #define MMCR_8042_ACTIVATE (*(VUINT8 *)(ADDR_8042_ACTIVATE))
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270 #define ADDR_8042_HOST_EC_DATACMD 0x400F0500
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271 #define MMCR_8042_HOST_EC_DATACMD (*(VUINT8 *)(ADDR_8042_HOST_EC_DATACMD))
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273 #define ADDR_8042_EC_HOST_DATA 0x400F0500
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274 #define MMCR_8042_EC_HOST_DATA (*(VUINT8 *)(ADDR_8042_EC_HOST_DATA))
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276 #define ADDR_8042_KEYBOARD_STATUS_READ 0x400F0504
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277 #define MMCR_8042_KEYBOARD_STATUS_READ (*(VUINT8 *)(ADDR_8042_KEYBOARD_STATUS_READ))
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279 #define ADDR_8042_KEYBOARD_CONTROL 0x400F0508
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280 #define MMCR_8042_KEYBOARD_CONTROL (*(VUINT8 *)(ADDR_8042_KEYBOARD_CONTROL))
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282 #define ADDR_8042_EC_HOST_AUX 0x400F050C
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283 #define MMCR_8042_EC_HOST_AUX (*(VUINT8 *)(ADDR_8042_EC_HOST_AUX))
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285 #define ADDR_8042_PCOBF 0x400F0514
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286 #define MMCR_8042_PCOBF (*(VUINT8 *)(ADDR_8042_PCOBF))
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288 #define ADDR_8042_PORT92_ENABLE 0x400F1B30
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289 #define MMCR_8042_PORT92_ENABLE (*(VUINT8 *)(ADDR_8042_PORT92_ENABLE))
\r
291 #define ADDR_8042_GATEA20_CONTROL 0x400F1900
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292 #define MMCR_8042_GATEA20_CONTROL (*(VUINT8 *)(ADDR_8042_GATEA20_CONTROL))
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294 #define ADDR_8042_SETGA20L 0x400F1908
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295 #define MMCR_8042_SETGA20L (*(VUINT8 *)(ADDR_8042_SETGA20L))
\r
297 #define ADDR_8042_RSTGA20L 0x400F190C
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298 #define MMCR_8042_RSTGA20L (*(VUINT8 *)(ADDR_8042_RSTGA20L))
\r
300 /***************************************************************
\r
302 ***************************************************************/
\r
303 #define ADDR_SMB_3_DEBUG_FSM_SMB 0x4000B45C
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304 #define MMCR_SMB_3_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_SMB))
\r
306 #define ADDR_SMB_3_DEBUG_FSM_I2C 0x4000B458
\r
307 #define MMCR_SMB_3_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_3_DEBUG_FSM_I2C))
\r
309 #define ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER 0x4000B454
\r
310 #define MMCR_SMBUS_3_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_RECEIVE_BUFFER))
\r
312 #define ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER 0x4000B450
\r
313 #define MMCR_SMBUS_3_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_3_MASTER_TRANSMIT_BUFER))
\r
315 #define ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER 0x4000B44C
\r
316 #define MMCR_SMBUS_3_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_RECEIVE_BUFFER))
\r
318 #define ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER 0x4000B448
\r
319 #define MMCR_SMBUS_3_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_3_SLAVE_TRANSMIT_BUFFER))
\r
321 #define ADDR_SMB_3_TIME_OUT_SCALING 0x4000B444
\r
322 #define MMCR_SMB_3_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_3_TIME_OUT_SCALING))
\r
324 #define ADDR_SMB_3_DATA_TIMING 0x4000B440
\r
325 #define MMCR_SMB_3_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_3_DATA_TIMING))
\r
327 #define ADDR_SMB_3_CLOCK_SYNC 0x4000B43C
\r
328 #define MMCR_SMB_3_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_3_CLOCK_SYNC))
\r
330 #define ADDR_SMB_3_BIT_BANG_CONTROL 0x4000B438
\r
331 #define MMCR_SMB_3_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_3_BIT_BANG_CONTROL))
\r
333 #define ADDR_SMB_3_REVISION 0x4000B434
\r
334 #define MMCR_SMB_3_REVISION (*(VUINT8 *)(ADDR_SMB_3_REVISION))
\r
336 #define ADDR_SMB_3_BLOCK_ID 0x4000B430
\r
337 #define MMCR_SMB_3_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_3_BLOCK_ID))
\r
339 #define ADDR_SMB_3_BUS_CLOCK 0x4000B42C
\r
340 #define MMCR_SMB_3_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_3_BUS_CLOCK))
\r
342 #define ADDR_SMB_3_CONFIGURATION 0x4000B428
\r
343 #define MMCR_SMB_3_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_3_CONFIGURATION))
\r
345 #define ADDR_SMB_3_IDLE_SCALING 0x4000B424
\r
346 #define MMCR_SMB_3_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_3_IDLE_SCALING))
\r
348 #define ADDR_SMB_3_COMPLETION 0x4000B420
\r
349 #define MMCR_SMB_3_COMPLETION (*(VUINT32 *)(ADDR_SMB_3_COMPLETION))
\r
351 #define ADDR_SMB_3_DATA_TIMING2 0x4000B418
\r
352 #define MMCR_SMB_3_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_3_DATA_TIMING2))
\r
354 #define ADDR_SMB_3_PEC 0x4000B414
\r
355 #define MMCR_SMB_3_PEC (*(VUINT8 *)(ADDR_SMB_3_PEC))
\r
357 #define ADDR_SMBUS_3_SLAVE_COMMAND 0x4000B410
\r
358 #define MMCR_SMBUS_3_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_SLAVE_COMMAND))
\r
360 #define ADDR_SMBUS_3_MASTER_COMMAND 0x4000B40C
\r
361 #define MMCR_SMBUS_3_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_3_MASTER_COMMAND))
\r
363 #define ADDR_SMB_3_DATA 0x4000B408
\r
364 #define MMCR_SMB_3_DATA (*(VUINT8 *)(ADDR_SMB_3_DATA))
\r
366 #define ADDR_SMB_3_OWN_ADDRESS 0x4000B404
\r
367 #define MMCR_SMB_3_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_3_OWN_ADDRESS))
\r
369 #define ADDR_SMB_3_STATUS 0x4000B400
\r
370 #define MMCR_SMB_3_STATUS (*(VUINT8 *)(ADDR_SMB_3_STATUS))
\r
372 #define ADDR_SMB_3_CONTROL 0x4000B400
\r
373 #define MMCR_SMB_3_CONTROL (*(VUINT8 *)(ADDR_SMB_3_CONTROL))
\r
375 #define ADDR_SMB_2_CONTROL 0x4000B000
\r
376 #define MMCR_SMB_2_CONTROL (*(VUINT8 *)(ADDR_SMB_2_CONTROL))
\r
378 #define ADDR_SMB_2_STATUS 0x4000B000
\r
379 #define MMCR_SMB_2_STATUS (*(VUINT8 *)(ADDR_SMB_2_STATUS))
\r
381 #define ADDR_SMB_2_OWN_ADDRESS 0x4000B004
\r
382 #define MMCR_SMB_2_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_2_OWN_ADDRESS))
\r
384 #define ADDR_SMB_2_DATA 0x4000B008
\r
385 #define MMCR_SMB_2_DATA (*(VUINT8 *)(ADDR_SMB_2_DATA))
\r
387 #define ADDR_SMBUS_2_MASTER_COMMAND 0x4000B00C
\r
388 #define MMCR_SMBUS_2_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_MASTER_COMMAND))
\r
390 #define ADDR_SMBUS_2_SLAVE_COMMAND 0x4000B010
\r
391 #define MMCR_SMBUS_2_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_2_SLAVE_COMMAND))
\r
393 #define ADDR_SMB_2_PEC 0x4000B014
\r
394 #define MMCR_SMB_2_PEC (*(VUINT8 *)(ADDR_SMB_2_PEC))
\r
396 #define ADDR_SMB_2_DATA_TIMING2 0x4000B018
\r
397 #define MMCR_SMB_2_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_2_DATA_TIMING2))
\r
399 #define ADDR_SMB_2_COMPLETION 0x4000B020
\r
400 #define MMCR_SMB_2_COMPLETION (*(VUINT32 *)(ADDR_SMB_2_COMPLETION))
\r
402 #define ADDR_SMB_2_IDLE_SCALING 0x4000B024
\r
403 #define MMCR_SMB_2_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_2_IDLE_SCALING))
\r
405 #define ADDR_SMB_2_CONFIGURATION 0x4000B028
\r
406 #define MMCR_SMB_2_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_2_CONFIGURATION))
\r
408 #define ADDR_SMB_2_BUS_CLOCK 0x4000B02C
\r
409 #define MMCR_SMB_2_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_2_BUS_CLOCK))
\r
411 #define ADDR_SMB_2_BLOCK_ID 0x4000B030
\r
412 #define MMCR_SMB_2_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_2_BLOCK_ID))
\r
414 #define ADDR_SMB_2_REVISION 0x4000B034
\r
415 #define MMCR_SMB_2_REVISION (*(VUINT8 *)(ADDR_SMB_2_REVISION))
\r
417 #define ADDR_SMB_2_BIT_BANG_CONTROL 0x4000B038
\r
418 #define MMCR_SMB_2_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_2_BIT_BANG_CONTROL))
\r
420 #define ADDR_SMB_2_CLOCK_SYNC 0x4000B03C
\r
421 #define MMCR_SMB_2_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_2_CLOCK_SYNC))
\r
423 #define ADDR_SMB_2_DATA_TIMING 0x4000B040
\r
424 #define MMCR_SMB_2_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_2_DATA_TIMING))
\r
426 #define ADDR_SMB_2_TIME_OUT_SCALING 0x4000B044
\r
427 #define MMCR_SMB_2_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_2_TIME_OUT_SCALING))
\r
429 #define ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER 0x4000B048
\r
430 #define MMCR_SMBUS_2_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_TRANSMIT_BUFFER))
\r
432 #define ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER 0x4000B04C
\r
433 #define MMCR_SMBUS_2_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_SLAVE_RECEIVE_BUFFER))
\r
435 #define ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER 0x4000B050
\r
436 #define MMCR_SMBUS_2_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_TRANSMIT_BUFER))
\r
438 #define ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER 0x4000B054
\r
439 #define MMCR_SMBUS_2_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_2_MASTER_RECEIVE_BUFFER))
\r
441 #define ADDR_SMB_2_DEBUG_FSM_I2C 0x4000B058
\r
442 #define MMCR_SMB_2_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_I2C))
\r
444 #define ADDR_SMB_2_DEBUG_FSM_SMB 0x4000B05C
\r
445 #define MMCR_SMB_2_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_2_DEBUG_FSM_SMB))
\r
447 #define ADDR_SMB_1_CONTROL 0x4000AC00
\r
448 #define MMCR_SMB_1_CONTROL (*(VUINT8 *)(ADDR_SMB_1_CONTROL))
\r
450 #define ADDR_SMB_1_STATUS 0x4000AC00
\r
451 #define MMCR_SMB_1_STATUS (*(VUINT8 *)(ADDR_SMB_1_STATUS))
\r
453 #define ADDR_SMB_1_OWN_ADDRESS 0x4000AC04
\r
454 #define MMCR_SMB_1_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_1_OWN_ADDRESS))
\r
456 #define ADDR_SMB_1_DATA 0x4000AC08
\r
457 #define MMCR_SMB_1_DATA (*(VUINT8 *)(ADDR_SMB_1_DATA))
\r
459 #define ADDR_SMBUS_1_MASTER_COMMAND 0x4000AC0C
\r
460 #define MMCR_SMBUS_1_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_MASTER_COMMAND))
\r
462 #define ADDR_SMBUS_1_SLAVE_COMMAND 0x4000AC10
\r
463 #define MMCR_SMBUS_1_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_1_SLAVE_COMMAND))
\r
465 #define ADDR_SMB_1_PEC 0x4000AC14
\r
466 #define MMCR_SMB_1_PEC (*(VUINT8 *)(ADDR_SMB_1_PEC))
\r
468 #define ADDR_SMB_1_DATA_TIMING2 0x4000AC18
\r
469 #define MMCR_SMB_1_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_1_DATA_TIMING2))
\r
471 #define ADDR_SMB_1_COMPLETION 0x4000AC20
\r
472 #define MMCR_SMB_1_COMPLETION (*(VUINT32 *)(ADDR_SMB_1_COMPLETION))
\r
474 #define ADDR_SMB_1_IDLE_SCALING 0x4000AC24
\r
475 #define MMCR_SMB_1_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_1_IDLE_SCALING))
\r
477 #define ADDR_SMB_1_CONFIGURATION 0x4000AC28
\r
478 #define MMCR_SMB_1_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_1_CONFIGURATION))
\r
480 #define ADDR_SMB_1_BUS_CLOCK 0x4000AC2C
\r
481 #define MMCR_SMB_1_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_1_BUS_CLOCK))
\r
483 #define ADDR_SMB_1_BLOCK_ID 0x4000AC30
\r
484 #define MMCR_SMB_1_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_1_BLOCK_ID))
\r
486 #define ADDR_SMB_1_REVISION 0x4000AC34
\r
487 #define MMCR_SMB_1_REVISION (*(VUINT8 *)(ADDR_SMB_1_REVISION))
\r
489 #define ADDR_SMB_1_BIT_BANG_CONTROL 0x4000AC38
\r
490 #define MMCR_SMB_1_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_1_BIT_BANG_CONTROL))
\r
492 #define ADDR_SMB_1_CLOCK_SYNC 0x4000AC3C
\r
493 #define MMCR_SMB_1_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_1_CLOCK_SYNC))
\r
495 #define ADDR_SMB_1_DATA_TIMING 0x4000AC40
\r
496 #define MMCR_SMB_1_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_1_DATA_TIMING))
\r
498 #define ADDR_SMB_1_TIME_OUT_SCALING 0x4000AC44
\r
499 #define MMCR_SMB_1_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_1_TIME_OUT_SCALING))
\r
501 #define ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER 0x4000AC48
\r
502 #define MMCR_SMBUS_1_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_TRANSMIT_BUFFER))
\r
504 #define ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER 0x4000AC4C
\r
505 #define MMCR_SMBUS_1_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_SLAVE_RECEIVE_BUFFER))
\r
507 #define ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER 0x4000AC50
\r
508 #define MMCR_SMBUS_1_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_TRANSMIT_BUFER))
\r
510 #define ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER 0x4000AC54
\r
511 #define MMCR_SMBUS_1_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_1_MASTER_RECEIVE_BUFFER))
\r
513 #define ADDR_SMB_1_DEBUG_FSM_I2C 0x4000AC58
\r
514 #define MMCR_SMB_1_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_I2C))
\r
516 #define ADDR_SMB_1_DEBUG_FSM_SMB 0x4000AC5C
\r
517 #define MMCR_SMB_1_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_1_DEBUG_FSM_SMB))
\r
519 #define ADDR_SMB_0_STATUS 0x40001800
\r
520 #define MMCR_SMB_0_STATUS (*(VUINT8 *)(ADDR_SMB_0_STATUS))
\r
522 #define ADDR_SMB_0_CONTROL 0x40001800
\r
523 #define MMCR_SMB_0_CONTROL (*(VUINT8 *)(ADDR_SMB_0_CONTROL))
\r
525 #define ADDR_SMB_0_OWN_ADDRESS 0x40001804
\r
526 #define MMCR_SMB_0_OWN_ADDRESS (*(VUINT16 *)(ADDR_SMB_0_OWN_ADDRESS))
\r
528 #define ADDR_SMB_0_DATA 0x40001808
\r
529 #define MMCR_SMB_0_DATA (*(VUINT8 *)(ADDR_SMB_0_DATA))
\r
531 #define ADDR_SMBUS_0_MASTER_COMMAND 0x4000180C
\r
532 #define MMCR_SMBUS_0_MASTER_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_MASTER_COMMAND))
\r
534 #define ADDR_SMBUS_0_SLAVE_COMMAND 0x40001810
\r
535 #define MMCR_SMBUS_0_SLAVE_COMMAND (*(VUINT32 *)(ADDR_SMBUS_0_SLAVE_COMMAND))
\r
537 #define ADDR_SMB_0_PEC 0x40001814
\r
538 #define MMCR_SMB_0_PEC (*(VUINT8 *)(ADDR_SMB_0_PEC))
\r
540 #define ADDR_SMB_0_DATA_TIMING2 0x40001818
\r
541 #define MMCR_SMB_0_DATA_TIMING2 (*(VUINT8 *)(ADDR_SMB_0_DATA_TIMING2))
\r
543 #define ADDR_SMB_0_COMPLETION 0x40001820
\r
544 #define MMCR_SMB_0_COMPLETION (*(VUINT32 *)(ADDR_SMB_0_COMPLETION))
\r
546 #define ADDR_SMB_0_IDLE_SCALING 0x40001824
\r
547 #define MMCR_SMB_0_IDLE_SCALING (*(VUINT32 *)(ADDR_SMB_0_IDLE_SCALING))
\r
549 #define ADDR_SMB_0_CONFIGURATION 0x40001828
\r
550 #define MMCR_SMB_0_CONFIGURATION (*(VUINT32 *)(ADDR_SMB_0_CONFIGURATION))
\r
552 #define ADDR_SMB_0_BUS_CLOCK 0x4000182C
\r
553 #define MMCR_SMB_0_BUS_CLOCK (*(VUINT16 *)(ADDR_SMB_0_BUS_CLOCK))
\r
555 #define ADDR_SMB_0_BLOCK_ID 0x40001830
\r
556 #define MMCR_SMB_0_BLOCK_ID (*(VUINT8 *)(ADDR_SMB_0_BLOCK_ID))
\r
558 #define ADDR_SMB_0_REVISION 0x40001834
\r
559 #define MMCR_SMB_0_REVISION (*(VUINT8 *)(ADDR_SMB_0_REVISION))
\r
561 #define ADDR_SMB_0_BIT_BANG_CONTROL 0x40001838
\r
562 #define MMCR_SMB_0_BIT_BANG_CONTROL (*(VUINT8 *)(ADDR_SMB_0_BIT_BANG_CONTROL))
\r
564 #define ADDR_SMB_0_CLOCK_SYNC 0x4000183C
\r
565 #define MMCR_SMB_0_CLOCK_SYNC (*(VUINT32 *)(ADDR_SMB_0_CLOCK_SYNC))
\r
567 #define ADDR_SMB_0_DATA_TIMING 0x40001840
\r
568 #define MMCR_SMB_0_DATA_TIMING (*(VUINT32 *)(ADDR_SMB_0_DATA_TIMING))
\r
570 #define ADDR_SMB_0_TIME_OUT_SCALING 0x40001844
\r
571 #define MMCR_SMB_0_TIME_OUT_SCALING (*(VUINT32 *)(ADDR_SMB_0_TIME_OUT_SCALING))
\r
573 #define ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER 0x40001848
\r
574 #define MMCR_SMBUS_0_SLAVE_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_TRANSMIT_BUFFER))
\r
576 #define ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER 0x4000184C
\r
577 #define MMCR_SMBUS_0_SLAVE_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_SLAVE_RECEIVE_BUFFER))
\r
579 #define ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER 0x40001850
\r
580 #define MMCR_SMBUS_0_MASTER_TRANSMIT_BUFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_TRANSMIT_BUFER))
\r
582 #define ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER 0x40001854
\r
583 #define MMCR_SMBUS_0_MASTER_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_SMBUS_0_MASTER_RECEIVE_BUFFER))
\r
585 #define ADDR_SMB_0_DEBUG_FSM_I2C 0x40001858
\r
586 #define MMCR_SMB_0_DEBUG_FSM_I2C (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_I2C))
\r
588 #define ADDR_SMB_0_DEBUG_FSM_SMB 0x4000185C
\r
589 #define MMCR_SMB_0_DEBUG_FSM_SMB (*(VUINT32 *)(ADDR_SMB_0_DEBUG_FSM_SMB))
\r
591 /***************************************************************
\r
592 * Watchdog Timer Interface
\r
593 ***************************************************************/
\r
594 #define ADDR_WATCHDOG_WDT_LOAD 0x40000400
\r
595 #define MMCR_WATCHDOG_WDT_LOAD (*(VUINT16 *)(ADDR_WATCHDOG_WDT_LOAD))
\r
597 #define ADDR_WATCHDOG_WDT_CONTROL 0x40000404
\r
598 #define MMCR_WATCHDOG_WDT_CONTROL (*(VUINT8 *)(ADDR_WATCHDOG_WDT_CONTROL))
\r
600 #define ADDR_WATCHDOG_WDT_KICK 0x40000408
\r
601 #define MMCR_WATCHDOG_WDT_KICK (*(VUINT8 *)(ADDR_WATCHDOG_WDT_KICK))
\r
603 #define ADDR_WATCHDOG_WDT_COUNT 0x4000040C
\r
604 #define MMCR_WATCHDOG_WDT_COUNT (*(VUINT16 *)(ADDR_WATCHDOG_WDT_COUNT))
\r
606 /***************************************************************
\r
608 ***************************************************************/
\r
609 #define ADDR_ACPI_0_PM1_STATUS_1 0x400F1500
\r
610 #define MMCR_ACPI_0_PM1_STATUS_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_1))
\r
612 #define ADDR_ACPI_0_PM1_STATUS_2 0x400F1501
\r
613 #define MMCR_ACPI_0_PM1_STATUS_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_STATUS_2))
\r
615 #define ADDR_ACPI_0_PM1_ENABLE_1 0x400F1502
\r
616 #define MMCR_ACPI_0_PM1_ENABLE_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_1))
\r
618 #define ADDR_ACPI_0_PM1_ENABLE_2 0x400F1503
\r
619 #define MMCR_ACPI_0_PM1_ENABLE_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_ENABLE_2))
\r
621 #define ADDR_ACPI_0_PM1_CONTROL_1 0x400F1504
\r
622 #define MMCR_ACPI_0_PM1_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_1))
\r
624 #define ADDR_ACPI_0_PM1_CONTROL_2 0x400F1505
\r
625 #define MMCR_ACPI_0_PM1_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM1_CONTROL_2))
\r
627 #define ADDR_ACPI_0_PM2_CONTROL_1 0x400F1506
\r
628 #define MMCR_ACPI_0_PM2_CONTROL_1 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_1))
\r
630 #define ADDR_ACPI_0_PM2_CONTROL_2 0x400F1507
\r
631 #define MMCR_ACPI_0_PM2_CONTROL_2 (*(VUINT8 *)(ADDR_ACPI_0_PM2_CONTROL_2))
\r
633 #define ADDR_ACPI_0_PM1_EC_PM_STATUS 0x400F1510
\r
634 #define MMCR_ACPI_0_PM1_EC_PM_STATUS (*(VUINT8 *)(ADDR_ACPI_0_PM1_EC_PM_STATUS))
\r
636 /***************************************************************
\r
638 ***************************************************************/
\r
639 #define ADDR_EC_1_SPI_CLOCK_GENERATOR 0x40009498
\r
640 #define MMCR_EC_1_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_GENERATOR))
\r
642 #define ADDR_EC_1_SPI_CLOCK_CONTROL 0x40009494
\r
643 #define MMCR_EC_1_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CLOCK_CONTROL))
\r
645 #define ADDR_EC_1_SPI_RX_DATA 0x40009490
\r
646 #define MMCR_EC_1_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_RX_DATA))
\r
648 #define ADDR_EC_1_SPI_TX_DATA 0x4000948C
\r
649 #define MMCR_EC_1_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_1_SPI_TX_DATA))
\r
651 #define ADDR_EC_1_SPI_STATUS 0x40009488
\r
652 #define MMCR_EC_1_SPI_STATUS (*(VUINT32 *)(ADDR_EC_1_SPI_STATUS))
\r
654 #define ADDR_EC_1_SPI_CONTROL 0x40009484
\r
655 #define MMCR_EC_1_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_1_SPI_CONTROL))
\r
657 #define ADDR_EC_1_SPI_ENABLE 0x40009480
\r
658 #define MMCR_EC_1_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_1_SPI_ENABLE))
\r
660 #define ADDR_EC_0_SPI_ENABLE 0x40009400
\r
661 #define MMCR_EC_0_SPI_ENABLE (*(VUINT32 *)(ADDR_EC_0_SPI_ENABLE))
\r
663 #define ADDR_EC_0_SPI_CONTROL 0x40009404
\r
664 #define MMCR_EC_0_SPI_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CONTROL))
\r
666 #define ADDR_EC_0_SPI_STATUS 0x40009408
\r
667 #define MMCR_EC_0_SPI_STATUS (*(VUINT32 *)(ADDR_EC_0_SPI_STATUS))
\r
669 #define ADDR_EC_0_SPI_TX_DATA 0x4000940C
\r
670 #define MMCR_EC_0_SPI_TX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_TX_DATA))
\r
672 #define ADDR_EC_0_SPI_RX_DATA 0x40009410
\r
673 #define MMCR_EC_0_SPI_RX_DATA (*(VUINT32 *)(ADDR_EC_0_SPI_RX_DATA))
\r
675 #define ADDR_EC_0_SPI_CLOCK_CONTROL 0x40009414
\r
676 #define MMCR_EC_0_SPI_CLOCK_CONTROL (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_CONTROL))
\r
678 #define ADDR_EC_0_SPI_CLOCK_GENERATOR 0x40009418
\r
679 #define MMCR_EC_0_SPI_CLOCK_GENERATOR (*(VUINT32 *)(ADDR_EC_0_SPI_CLOCK_GENERATOR))
\r
681 /***************************************************************
\r
682 * Mailbox Registers Interface
\r
683 ***************************************************************/
\r
684 #define ADDR_MAILBOX_HOST_TO_EC_MAILBOX 0x400F2500
\r
685 #define MMCR_MAILBOX_HOST_TO_EC_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_HOST_TO_EC_MAILBOX))
\r
687 #define ADDR_MAILBOX_EC_TO_HOST_MAILBOX 0x400F2504
\r
688 #define MMCR_MAILBOX_EC_TO_HOST_MAILBOX (*(VUINT32 *)(ADDR_MAILBOX_EC_TO_HOST_MAILBOX))
\r
690 #define ADDR_MAILBOX_SMI_INTERRUPT_SOURCE 0x400F2508
\r
691 #define MMCR_MAILBOX_SMI_INTERRUPT_SOURCE (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_SOURCE))
\r
693 #define ADDR_MAILBOX_SMI_INTERRUPT_MASK 0x400F250C
\r
694 #define MMCR_MAILBOX_SMI_INTERRUPT_MASK (*(VUINT32 *)(ADDR_MAILBOX_SMI_INTERRUPT_MASK))
\r
696 #define ADDR_MAILBOX_3_0 0x400F2510
\r
697 #define MMCR_MAILBOX_3_0 (*(VUINT32 *)(ADDR_MAILBOX_3_0))
\r
699 #define ADDR_MAILBOX_7_4 0x400F2514
\r
700 #define MMCR_MAILBOX_7_4 (*(VUINT32 *)(ADDR_MAILBOX_7_4))
\r
702 #define ADDR_MAILBOX_BH_8 0x400F2518
\r
703 #define MMCR_MAILBOX_BH_8 (*(VUINT32 *)(ADDR_MAILBOX_BH_8))
\r
705 #define ADDR_MAILBOX_FH_CH 0x400F251C
\r
706 #define MMCR_MAILBOX_FH_CH (*(VUINT32 *)(ADDR_MAILBOX_FH_CH))
\r
708 #define ADDR_MAILBOX_13H_10H 0x400F2520
\r
709 #define MMCR_MAILBOX_13H_10H (*(VUINT32 *)(ADDR_MAILBOX_13H_10H))
\r
711 #define ADDR_MAILBOX_17H_14H 0x400F2524
\r
712 #define MMCR_MAILBOX_17H_14H (*(VUINT32 *)(ADDR_MAILBOX_17H_14H))
\r
714 #define ADDR_MAILBOX_1BH_18H 0x400F2528
\r
715 #define MMCR_MAILBOX_1BH_18H (*(VUINT32 *)(ADDR_MAILBOX_1BH_18H))
\r
717 #define ADDR_MAILBOX_1FH_1CH 0x400F252C
\r
718 #define MMCR_MAILBOX_1FH_1CH (*(VUINT32 *)(ADDR_MAILBOX_1FH_1CH))
\r
720 /***************************************************************
\r
721 * Hibernation Timer
\r
722 ***************************************************************/
\r
723 #define ADDR_HIBERNATION_0_HTIMER_X_PRELOAD 0x40009800
\r
724 #define MMCR_HIBERNATION_0_HTIMER_X_PRELOAD (*(VUINT16 *)(ADDR_HIBERNATION_0_HTIMER_X_PRELOAD))
\r
726 #define ADDR_HIBERNATION_0_TIMER_X_CONTROL 0x40009804
\r
727 #define MMCR_HIBERNATION_0_TIMER_X_CONTROL (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_CONTROL))
\r
729 #define ADDR_HIBERNATION_0_TIMER_X_COUNT 0x40009808
\r
730 #define MMCR_HIBERNATION_0_TIMER_X_COUNT (*(VUINT16 *)(ADDR_HIBERNATION_0_TIMER_X_COUNT))
\r
732 /***************************************************************
\r
734 ***************************************************************/
\r
735 #define ADDR_M16C550A_UART_ACTIVATE 0x400F1F30
\r
736 #define MMCR_M16C550A_UART_ACTIVATE (*(VUINT8 *)(ADDR_M16C550A_UART_ACTIVATE))
\r
738 #define ADDR_M16C550A_UART_CONFIG_SELECT 0x400F1FF0
\r
739 #define MMCR_M16C550A_UART_CONFIG_SELECT (*(VUINT8 *)(ADDR_M16C550A_UART_CONFIG_SELECT))
\r
741 #define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB 0x400F1D00
\r
742 #define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_LSB))
\r
744 #define ADDR_M16C550A_UART_RECEIVE_BUFFER 0x400F1D00
\r
745 #define MMCR_M16C550A_UART_RECEIVE_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_RECEIVE_BUFFER))
\r
747 #define ADDR_M16C550A_UART_TRANSMIT_BUFFER 0x400F1D00
\r
748 #define MMCR_M16C550A_UART_TRANSMIT_BUFFER (*(VUINT8 *)(ADDR_M16C550A_UART_TRANSMIT_BUFFER))
\r
750 #define ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB 0x400F1D01
\r
751 #define MMCR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB (*(VUINT8 *)(ADDR_M16C550A_UART_PROGRAMMABLE_BAUD_RATE_GENERATOR_MSB))
\r
753 #define ADDR_M16C550A_UART_INTERRUPT_ENABLE 0x400F1D01
\r
754 #define MMCR_M16C550A_UART_INTERRUPT_ENABLE (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_ENABLE))
\r
756 #define ADDR_M16C550A_UART_FIFO_CONTROL 0x400F1D02
\r
757 #define MMCR_M16C550A_UART_FIFO_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_FIFO_CONTROL))
\r
759 #define ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION 0x400F1D02
\r
760 #define MMCR_M16C550A_UART_INTERRUPT_IDENTIFICATION (*(VUINT8 *)(ADDR_M16C550A_UART_INTERRUPT_IDENTIFICATION))
\r
762 #define ADDR_M16C550A_UART_LINE_CONTROL 0x400F1D03
\r
763 #define MMCR_M16C550A_UART_LINE_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_CONTROL))
\r
765 #define ADDR_M16C550A_UART_MODEM_CONTROL 0x400F1D04
\r
766 #define MMCR_M16C550A_UART_MODEM_CONTROL (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_CONTROL))
\r
768 #define ADDR_M16C550A_UART_LINE_STATUS 0x400F1D05
\r
769 #define MMCR_M16C550A_UART_LINE_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_LINE_STATUS))
\r
771 #define ADDR_M16C550A_UART_MODEM_STATUS 0x400F1D06
\r
772 #define MMCR_M16C550A_UART_MODEM_STATUS (*(VUINT8 *)(ADDR_M16C550A_UART_MODEM_STATUS))
\r
774 #define ADDR_M16C550A_UART_SCRATCHPAD 0x400F1D07
\r
775 #define MMCR_M16C550A_UART_SCRATCHPAD (*(VUINT8 *)(ADDR_M16C550A_UART_SCRATCHPAD))
\r
777 /***************************************************************
\r
779 ***************************************************************/
\r
780 #define ADDR_TACH_0_CONTROL 0x40006000
\r
781 #define MMCR_TACH_0_CONTROL (*(VUINT32 *)(ADDR_TACH_0_CONTROL))
\r
783 #define ADDR_TACH_0_STATUS 0x40006004
\r
784 #define MMCR_TACH_0_STATUS (*(VUINT32 *)(ADDR_TACH_0_STATUS))
\r
786 #define ADDR_TACH_0_HIGH_LIMIT 0x40006008
\r
787 #define MMCR_TACH_0_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_0_HIGH_LIMIT))
\r
789 #define ADDR_TACH_0_LOW_LIMIT 0x4000600C
\r
790 #define MMCR_TACH_0_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_0_LOW_LIMIT))
\r
792 #define ADDR_TACH_1_CONTROL 0x40006010
\r
793 #define MMCR_TACH_1_CONTROL (*(VUINT32 *)(ADDR_TACH_1_CONTROL))
\r
795 #define ADDR_TACH_1_STATUS 0x40006014
\r
796 #define MMCR_TACH_1_STATUS (*(VUINT32 *)(ADDR_TACH_1_STATUS))
\r
798 #define ADDR_TACH_1_HIGH_LIMIT 0x40006018
\r
799 #define MMCR_TACH_1_HIGH_LIMIT (*(VUINT32 *)(ADDR_TACH_1_HIGH_LIMIT))
\r
801 #define ADDR_TACH_1_LOW_LIMIT 0x4000601C
\r
802 #define MMCR_TACH_1_LOW_LIMIT (*(VUINT32 *)(ADDR_TACH_1_LOW_LIMIT))
\r
804 /***************************************************************
\r
805 * Global Config Regs Basic
\r
806 ***************************************************************/
\r
807 #define ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER 0x400FFF07
\r
808 #define MMCR_GLOBAL_LOGICAL_DEVICE_NUMBER (*(VUINT8 *)(ADDR_GLOBAL_LOGICAL_DEVICE_NUMBER))
\r
810 #define ADDR_GLOBAL_DEVICE_ID 0x400FFF20
\r
811 #define MMCR_GLOBAL_DEVICE_ID (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_ID))
\r
813 #define ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED 0x400FFF21
\r
814 #define MMCR_GLOBAL_DEVICE_REVISION_HARD_WIRED (*(VUINT8 *)(ADDR_GLOBAL_DEVICE_REVISION_HARD_WIRED))
\r
816 #define ADDR_GLOBAL_GCR_BUILD 0x400FFF28
\r
817 #define MMCR_GLOBAL_GCR_BUILD (*(VUINT16 *)(ADDR_GLOBAL_GCR_BUILD))
\r
819 #define ADDR_GLOBAL_GCR_SCRATCH 0x400FFF2C
\r
820 #define MMCR_GLOBAL_GCR_SCRATCH (*(VUINT32 *)(ADDR_GLOBAL_GCR_SCRATCH))
\r
822 /***************************************************************
\r
823 * Trace FIFO Debug Port
\r
824 ***************************************************************/
\r
825 #define ADDR_TRACE_DATA 0x40008C00
\r
826 #define MMCR_TRACE_DATA (*(VUINT32 *)(ADDR_TRACE_DATA))
\r
828 #define ADDR_TRACE_CONTROL 0x40008C04
\r
829 #define MMCR_TRACE_CONTROL (*(VUINT32 *)(ADDR_TRACE_CONTROL))
\r
831 /***************************************************************
\r
833 ***************************************************************/
\r
834 #define ADDR_STAP_MESSAGE_OBF 0x40080000
\r
835 #define MMCR_STAP_MESSAGE_OBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_OBF))
\r
837 #define ADDR_STAP_MESSAGE_IBF 0x40080004
\r
838 #define MMCR_STAP_MESSAGE_IBF (*(VUINT32 *)(ADDR_STAP_MESSAGE_IBF))
\r
840 #define ADDR_STAP_OBF_STATUS 0x40080008
\r
841 #define MMCR_STAP_OBF_STATUS (*(VUINT8 *)(ADDR_STAP_OBF_STATUS))
\r
843 #define ADDR_STAP_IBF_STATUS 0x40080009
\r
844 #define MMCR_STAP_IBF_STATUS (*(VUINT8 *)(ADDR_STAP_IBF_STATUS))
\r
846 #define ADDR_STAP_DBG_CTRL 0x4008000C
\r
847 #define MMCR_STAP_DBG_CTRL (*(VUINT8 *)(ADDR_STAP_DBG_CTRL))
\r
849 /***************************************************************
\r
851 ***************************************************************/
\r
852 #define ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX 0x400F0100
\r
853 #define MMCR_IMAP_EMI_HOST_TO_EC_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EMI_HOST_TO_EC_MAILBOX))
\r
855 #define ADDR_IMAP_EC_TO_HOST_MAILBOX 0x400F0101
\r
856 #define MMCR_IMAP_EC_TO_HOST_MAILBOX (*(VUINT8 *)(ADDR_IMAP_EC_TO_HOST_MAILBOX))
\r
858 #define ADDR_IMAP_MEMORY_BASE_ADDRESS_0 0x400F0104
\r
859 #define MMCR_IMAP_MEMORY_BASE_ADDRESS_0 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_0))
\r
861 #define ADDR_IMAP_MEMORY_READ_LIMIT_0 0x400F0108
\r
862 #define MMCR_IMAP_MEMORY_READ_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_0))
\r
864 #define ADDR_IMAP_MEMORY_WRITE_LIMIT_0 0x400F010A
\r
865 #define MMCR_IMAP_MEMORY_WRITE_LIMIT_0 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_0))
\r
867 #define ADDR_IMAP_MEMORY_BASE_ADDRESS_1 0x400F010C
\r
868 #define MMCR_IMAP_MEMORY_BASE_ADDRESS_1 (*(VUINT32 *)(ADDR_IMAP_MEMORY_BASE_ADDRESS_1))
\r
870 #define ADDR_IMAP_MEMORY_READ_LIMIT_1 0x400F0110
\r
871 #define MMCR_IMAP_MEMORY_READ_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_READ_LIMIT_1))
\r
873 #define ADDR_IMAP_MEMORY_WRITE_LIMIT_1 0x400F0112
\r
874 #define MMCR_IMAP_MEMORY_WRITE_LIMIT_1 (*(VUINT16 *)(ADDR_IMAP_MEMORY_WRITE_LIMIT_1))
\r
876 #define ADDR_IMAP_INTERRUPT_SET 0x400F0114
\r
877 #define MMCR_IMAP_INTERRUPT_SET (*(VUINT16 *)(ADDR_IMAP_INTERRUPT_SET))
\r
879 #define ADDR_IMAP_HOST_CLEAR_ENABLE 0x400F0116
\r
880 #define MMCR_IMAP_HOST_CLEAR_ENABLE (*(VUINT16 *)(ADDR_IMAP_HOST_CLEAR_ENABLE))
\r
882 /***************************************************************
\r
883 * Blinking/Breathing PWM
\r
884 ***************************************************************/
\r
885 #define ADDR_LED_3_UPDATE_INTERVAL 0x4000BB10
\r
886 #define MMCR_LED_3_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_3_UPDATE_INTERVAL))
\r
888 #define ADDR_LED_3_UPDATE_STEPSIZE 0x4000BB0C
\r
889 #define MMCR_LED_3_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_3_UPDATE_STEPSIZE))
\r
891 #define ADDR_LED_3_DELAY 0x4000BB08
\r
892 #define MMCR_LED_3_DELAY (*(VUINT32 *)(ADDR_LED_3_DELAY))
\r
894 #define ADDR_LED_3_LIMITS 0x4000BB04
\r
895 #define MMCR_LED_3_LIMITS (*(VUINT32 *)(ADDR_LED_3_LIMITS))
\r
897 #define ADDR_LED_3_CONFIGURATION 0x4000BB00
\r
898 #define MMCR_LED_3_CONFIGURATION (*(VUINT32 *)(ADDR_LED_3_CONFIGURATION))
\r
900 #define ADDR_LED_2_UPDATE_INTERVAL 0x4000BA10
\r
901 #define MMCR_LED_2_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_2_UPDATE_INTERVAL))
\r
903 #define ADDR_LED_2_UPDATE_STEPSIZE 0x4000BA0C
\r
904 #define MMCR_LED_2_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_2_UPDATE_STEPSIZE))
\r
906 #define ADDR_LED_2_DELAY 0x4000BA08
\r
907 #define MMCR_LED_2_DELAY (*(VUINT32 *)(ADDR_LED_2_DELAY))
\r
909 #define ADDR_LED_2_LIMITS 0x4000BA04
\r
910 #define MMCR_LED_2_LIMITS (*(VUINT32 *)(ADDR_LED_2_LIMITS))
\r
912 #define ADDR_LED_2_CONFIGURATION 0x4000BA00
\r
913 #define MMCR_LED_2_CONFIGURATION (*(VUINT32 *)(ADDR_LED_2_CONFIGURATION))
\r
915 #define ADDR_LED_1_CONFIGURATION 0x4000B900
\r
916 #define MMCR_LED_1_CONFIGURATION (*(VUINT32 *)(ADDR_LED_1_CONFIGURATION))
\r
918 #define ADDR_LED_1_LIMITS 0x4000B904
\r
919 #define MMCR_LED_1_LIMITS (*(VUINT32 *)(ADDR_LED_1_LIMITS))
\r
921 #define ADDR_LED_1_DELAY 0x4000B908
\r
922 #define MMCR_LED_1_DELAY (*(VUINT32 *)(ADDR_LED_1_DELAY))
\r
924 #define ADDR_LED_1_UPDATE_STEPSIZE 0x4000B90C
\r
925 #define MMCR_LED_1_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_1_UPDATE_STEPSIZE))
\r
927 #define ADDR_LED_1_UPDATE_INTERVAL 0x4000B910
\r
928 #define MMCR_LED_1_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_1_UPDATE_INTERVAL))
\r
930 #define ADDR_LED_0_CONFIGURATION 0x4000B800
\r
931 #define MMCR_LED_0_CONFIGURATION (*(VUINT32 *)(ADDR_LED_0_CONFIGURATION))
\r
933 #define ADDR_LED_0_LIMITS 0x4000B804
\r
934 #define MMCR_LED_0_LIMITS (*(VUINT32 *)(ADDR_LED_0_LIMITS))
\r
936 #define ADDR_LED_0_DELAY 0x4000B808
\r
937 #define MMCR_LED_0_DELAY (*(VUINT32 *)(ADDR_LED_0_DELAY))
\r
939 #define ADDR_LED_0_UPDATE_STEPSIZE 0x4000B80C
\r
940 #define MMCR_LED_0_UPDATE_STEPSIZE (*(VUINT32 *)(ADDR_LED_0_UPDATE_STEPSIZE))
\r
942 #define ADDR_LED_0_UPDATE_INTERVAL 0x4000B810
\r
943 #define MMCR_LED_0_UPDATE_INTERVAL (*(VUINT32 *)(ADDR_LED_0_UPDATE_INTERVAL))
\r
945 /***************************************************************
\r
946 * SMSC BC-Link Master
\r
947 ***************************************************************/
\r
948 #define ADDR_BC_LINK_STATUS 0x4000BC00
\r
949 #define MMCR_BC_LINK_STATUS (*(VUINT8 *)(ADDR_BC_LINK_STATUS))
\r
951 #define ADDR_BC_LINK_ADDRESS 0x4000BC04
\r
952 #define MMCR_BC_LINK_ADDRESS (*(VUINT8 *)(ADDR_BC_LINK_ADDRESS))
\r
954 #define ADDR_BC_LINK_DATA 0x4000BC08
\r
955 #define MMCR_BC_LINK_DATA (*(VUINT8 *)(ADDR_BC_LINK_DATA))
\r
957 #define ADDR_BC_LINK_CLOCK_SELECT 0x4000BC0C
\r
958 #define MMCR_BC_LINK_CLOCK_SELECT (*(VUINT8 *)(ADDR_BC_LINK_CLOCK_SELECT))
\r
960 /***************************************************************
\r
962 ***************************************************************/
\r
963 #define ADDR_BASIC_0_TIMER_COUNT 0x40000C00
\r
964 #define MMCR_BASIC_0_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_0_TIMER_COUNT))
\r
966 #define ADDR_BASIC_0_TIMER_PRELOAD 0x40000C04
\r
967 #define MMCR_BASIC_0_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_0_TIMER_PRELOAD))
\r
969 #define ADDR_BASIC_0_TIMER_STATUS 0x40000C08
\r
970 #define MMCR_BASIC_0_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_0_TIMER_STATUS))
\r
972 #define ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE 0x40000C0C
\r
973 #define MMCR_BASIC_0_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_0_TIMER_INTERRUPT_ENABLE))
\r
975 #define ADDR_BASIC_0_TIMER_CONTROL 0x40000C10
\r
976 #define MMCR_BASIC_0_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_0_TIMER_CONTROL))
\r
978 #define ADDR_BASIC_1_TIMER_COUNT 0x40000C20
\r
979 #define MMCR_BASIC_1_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_1_TIMER_COUNT))
\r
981 #define ADDR_BASIC_1_TIMER_PRELOAD 0x40000C24
\r
982 #define MMCR_BASIC_1_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_1_TIMER_PRELOAD))
\r
984 #define ADDR_BASIC_1_TIMER_STATUS 0x40000C28
\r
985 #define MMCR_BASIC_1_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_1_TIMER_STATUS))
\r
987 #define ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE 0x40000C2C
\r
988 #define MMCR_BASIC_1_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_1_TIMER_INTERRUPT_ENABLE))
\r
990 #define ADDR_BASIC_1_TIMER_CONTROL 0x40000C30
\r
991 #define MMCR_BASIC_1_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_1_TIMER_CONTROL))
\r
993 #define ADDR_BASIC_2_TIMER_COUNT 0x40000C40
\r
994 #define MMCR_BASIC_2_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_2_TIMER_COUNT))
\r
996 #define ADDR_BASIC_2_TIMER_PRELOAD 0x40000C44
\r
997 #define MMCR_BASIC_2_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_2_TIMER_PRELOAD))
\r
999 #define ADDR_BASIC_2_TIMER_STATUS 0x40000C48
\r
1000 #define MMCR_BASIC_2_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_2_TIMER_STATUS))
\r
1002 #define ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE 0x40000C4C
\r
1003 #define MMCR_BASIC_2_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_2_TIMER_INTERRUPT_ENABLE))
\r
1005 #define ADDR_BASIC_2_TIMER_CONTROL 0x40000C50
\r
1006 #define MMCR_BASIC_2_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_2_TIMER_CONTROL))
\r
1008 #define ADDR_BASIC_3_TIMER_COUNT 0x40000C60
\r
1009 #define MMCR_BASIC_3_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_3_TIMER_COUNT))
\r
1011 #define ADDR_BASIC_3_TIMER_PRELOAD 0x40000C64
\r
1012 #define MMCR_BASIC_3_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_3_TIMER_PRELOAD))
\r
1014 #define ADDR_BASIC_3_TIMER_STATUS 0x40000C68
\r
1015 #define MMCR_BASIC_3_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_3_TIMER_STATUS))
\r
1017 #define ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE 0x40000C6C
\r
1018 #define MMCR_BASIC_3_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_3_TIMER_INTERRUPT_ENABLE))
\r
1020 #define ADDR_BASIC_3_TIMER_CONTROL 0x40000C70
\r
1021 #define MMCR_BASIC_3_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_3_TIMER_CONTROL))
\r
1023 #define ADDR_BASIC_4_TIMER_COUNT 0x40000C80
\r
1024 #define MMCR_BASIC_4_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_4_TIMER_COUNT))
\r
1026 #define ADDR_BASIC_4_TIMER_PRELOAD 0x40000C84
\r
1027 #define MMCR_BASIC_4_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_4_TIMER_PRELOAD))
\r
1029 #define ADDR_BASIC_4_TIMER_STATUS 0x40000C88
\r
1030 #define MMCR_BASIC_4_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_4_TIMER_STATUS))
\r
1032 #define ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE 0x40000C8C
\r
1033 #define MMCR_BASIC_4_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_4_TIMER_INTERRUPT_ENABLE))
\r
1035 #define ADDR_BASIC_4_TIMER_CONTROL 0x40000C90
\r
1036 #define MMCR_BASIC_4_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_4_TIMER_CONTROL))
\r
1038 #define ADDR_BASIC_5_TIMER_COUNT 0x40000CA0
\r
1039 #define MMCR_BASIC_5_TIMER_COUNT (*(VUINT32 *)(ADDR_BASIC_5_TIMER_COUNT))
\r
1041 #define ADDR_BASIC_5_TIMER_PRELOAD 0x40000CA4
\r
1042 #define MMCR_BASIC_5_TIMER_PRELOAD (*(VUINT32 *)(ADDR_BASIC_5_TIMER_PRELOAD))
\r
1044 #define ADDR_BASIC_5_TIMER_STATUS 0x40000CA8
\r
1045 #define MMCR_BASIC_5_TIMER_STATUS (*(VUINT32 *)(ADDR_BASIC_5_TIMER_STATUS))
\r
1047 #define ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE 0x40000CAC
\r
1048 #define MMCR_BASIC_5_TIMER_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_BASIC_5_TIMER_INTERRUPT_ENABLE))
\r
1050 #define ADDR_BASIC_5_TIMER_CONTROL 0x40000CB0
\r
1051 #define MMCR_BASIC_5_TIMER_CONTROL (*(VUINT32 *)(ADDR_BASIC_5_TIMER_CONTROL))
\r
1053 /***************************************************************
\r
1055 ***************************************************************/
\r
1056 #define ADDR_EC_GIRQ8_SOURCE 0x4000C000
\r
1057 #define MMCR_EC_GIRQ8_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ8_SOURCE))
\r
1059 #define ADDR_EC_GIRQ8_ENABLE_SET 0x4000C004
\r
1060 #define MMCR_EC_GIRQ8_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_SET))
\r
1062 #define ADDR_EC_GIRQ8_RESULT 0x4000C008
\r
1063 #define MMCR_EC_GIRQ8_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ8_RESULT))
\r
1065 #define ADDR_EC_GIRQ8_ENABLE_CLEAR 0x4000C00C
\r
1066 #define MMCR_EC_GIRQ8_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ8_ENABLE_CLEAR))
\r
1068 #define ADDR_EC_GIRQ9_SOURCE 0x4000C014
\r
1069 #define MMCR_EC_GIRQ9_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ9_SOURCE))
\r
1071 #define ADDR_EC_GIRQ9_ENABLE_SET 0x4000C018
\r
1072 #define MMCR_EC_GIRQ9_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_SET))
\r
1074 #define ADDR_EC_GIRQ9_RESULT 0x4000C01C
\r
1075 #define MMCR_EC_GIRQ9_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ9_RESULT))
\r
1077 #define ADDR_EC_GIRQ9_ENABLE_CLEAR 0x4000C020
\r
1078 #define MMCR_EC_GIRQ9_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ9_ENABLE_CLEAR))
\r
1080 #define ADDR_EC_GIRQ10_SOURCE 0x4000C028
\r
1081 #define MMCR_EC_GIRQ10_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ10_SOURCE))
\r
1083 #define ADDR_EC_GIRQ10_ENABLE_SET 0x4000C02C
\r
1084 #define MMCR_EC_GIRQ10_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_SET))
\r
1086 #define ADDR_EC_GIRQ10_RESULT 0x4000C030
\r
1087 #define MMCR_EC_GIRQ10_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ10_RESULT))
\r
1089 #define ADDR_EC_GIRQ10_ENABLE_CLEAR 0x4000C034
\r
1090 #define MMCR_EC_GIRQ10_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ10_ENABLE_CLEAR))
\r
1092 #define ADDR_EC_GIRQ11_SOURCE 0x4000C03C
\r
1093 #define MMCR_EC_GIRQ11_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ11_SOURCE))
\r
1095 #define ADDR_EC_GIRQ11_ENABLE_SET 0x4000C040
\r
1096 #define MMCR_EC_GIRQ11_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_SET))
\r
1098 #define ADDR_EC_GIRQ11_RESULT 0x4000C044
\r
1099 #define MMCR_EC_GIRQ11_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ11_RESULT))
\r
1101 #define ADDR_EC_GIRQ11_ENABLE_CLEAR 0x4000C048
\r
1102 #define MMCR_EC_GIRQ11_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ11_ENABLE_CLEAR))
\r
1104 #define ADDR_EC_GIRQ12_SOURCE 0x4000C050
\r
1105 #define MMCR_EC_GIRQ12_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ12_SOURCE))
\r
1107 #define ADDR_EC_GIRQ12_ENABLE_SET 0x4000C054
\r
1108 #define MMCR_EC_GIRQ12_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_SET))
\r
1110 #define ADDR_EC_GIRQ12_RESULT 0x4000C058
\r
1111 #define MMCR_EC_GIRQ12_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ12_RESULT))
\r
1113 #define ADDR_EC_GIRQ12_ENABLE_CLEAR 0x4000C05C
\r
1114 #define MMCR_EC_GIRQ12_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ12_ENABLE_CLEAR))
\r
1116 #define ADDR_EC_GIRQ13_SOURCE 0x4000C064
\r
1117 #define MMCR_EC_GIRQ13_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ13_SOURCE))
\r
1119 #define ADDR_EC_GIRQ13_ENABLE_SET 0x4000C068
\r
1120 #define MMCR_EC_GIRQ13_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_SET))
\r
1122 #define ADDR_EC_GIRQ13_RESULT 0x4000C06C
\r
1123 #define MMCR_EC_GIRQ13_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ13_RESULT))
\r
1125 #define ADDR_EC_GIRQ13_ENABLE_CLEAR 0x4000C070
\r
1126 #define MMCR_EC_GIRQ13_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ13_ENABLE_CLEAR))
\r
1128 #define ADDR_EC_GIRQ14_SOURCE 0x4000C078
\r
1129 #define MMCR_EC_GIRQ14_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ14_SOURCE))
\r
1131 #define ADDR_EC_GIRQ14_ENABLE_SET 0x4000C07C
\r
1132 #define MMCR_EC_GIRQ14_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_SET))
\r
1134 #define ADDR_EC_GIRQ14_RESULT 0x4000C080
\r
1135 #define MMCR_EC_GIRQ14_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ14_RESULT))
\r
1137 #define ADDR_EC_GIRQ14_ENABLE_CLEAR 0x4000C084
\r
1138 #define MMCR_EC_GIRQ14_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ14_ENABLE_CLEAR))
\r
1140 #define ADDR_EC_GIRQ15_SOURCE 0x4000C08C
\r
1141 #define MMCR_EC_GIRQ15_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ15_SOURCE))
\r
1143 #define ADDR_EC_GIRQ15_ENABLE_SET 0x4000C090
\r
1144 #define MMCR_EC_GIRQ15_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_SET))
\r
1146 #define ADDR_EC_GIRQ15_RESULT 0x4000C094
\r
1147 #define MMCR_EC_GIRQ15_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ15_RESULT))
\r
1149 #define ADDR_EC_GIRQ15_ENABLE_CLEAR 0x4000C098
\r
1150 #define MMCR_EC_GIRQ15_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ15_ENABLE_CLEAR))
\r
1152 #define ADDR_EC_GIRQ16_SOURCE 0x4000C0A0
\r
1153 #define MMCR_EC_GIRQ16_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ16_SOURCE))
\r
1155 #define ADDR_EC_GIRQ16_ENABLE_SET 0x4000C0A4
\r
1156 #define MMCR_EC_GIRQ16_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_SET))
\r
1158 #define ADDR_EC_GIRQ16_RESULT 0x4000C0A8
\r
1159 #define MMCR_EC_GIRQ16_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ16_RESULT))
\r
1161 #define ADDR_EC_GIRQ16_ENABLE_CLEAR 0x4000C0AC
\r
1162 #define MMCR_EC_GIRQ16_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ16_ENABLE_CLEAR))
\r
1164 #define ADDR_EC_GIRQ17_SOURCE 0x4000C0B4
\r
1165 #define MMCR_EC_GIRQ17_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ17_SOURCE))
\r
1167 #define ADDR_EC_GIRQ17_ENABLE_SET 0x4000C0B8
\r
1168 #define MMCR_EC_GIRQ17_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_SET))
\r
1170 #define ADDR_EC_GIRQ17_RESULT 0x4000C0BC
\r
1171 #define MMCR_EC_GIRQ17_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ17_RESULT))
\r
1173 #define ADDR_EC_GIRQ17_ENABLE_CLEAR 0x4000C0C0
\r
1174 #define MMCR_EC_GIRQ17_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ17_ENABLE_CLEAR))
\r
1176 #define ADDR_EC_GIRQ18_SOURCE 0x4000C0C8
\r
1177 #define MMCR_EC_GIRQ18_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ18_SOURCE))
\r
1179 #define ADDR_EC_GIRQ18_ENABLE_SET 0x4000C0CC
\r
1180 #define MMCR_EC_GIRQ18_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_SET))
\r
1182 #define ADDR_EC_GIRQ18_RESULT 0x4000C0D0
\r
1183 #define MMCR_EC_GIRQ18_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ18_RESULT))
\r
1185 #define ADDR_EC_GIRQ18_ENABLE_CLEAR 0x4000C0D4
\r
1186 #define MMCR_EC_GIRQ18_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ18_ENABLE_CLEAR))
\r
1188 #define ADDR_EC_GIRQ19_SOURCE 0x4000C0DC
\r
1189 #define MMCR_EC_GIRQ19_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ19_SOURCE))
\r
1191 #define ADDR_EC_GIRQ19_ENABLE_SET 0x4000C0E0
\r
1192 #define MMCR_EC_GIRQ19_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_SET))
\r
1194 #define ADDR_EC_GIRQ19_RESULT 0x4000C0E4
\r
1195 #define MMCR_EC_GIRQ19_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ19_RESULT))
\r
1197 #define ADDR_EC_GIRQ19_ENABLE_CLEAR 0x4000C0E8
\r
1198 #define MMCR_EC_GIRQ19_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ19_ENABLE_CLEAR))
\r
1200 #define ADDR_EC_GIRQ20_SOURCE 0x4000C0F0
\r
1201 #define MMCR_EC_GIRQ20_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ20_SOURCE))
\r
1203 #define ADDR_EC_GIRQ20_ENABLE_SET 0x4000C0F4
\r
1204 #define MMCR_EC_GIRQ20_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_SET))
\r
1206 #define ADDR_EC_GIRQ20_RESULT 0x4000C0F8
\r
1207 #define MMCR_EC_GIRQ20_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ20_RESULT))
\r
1209 #define ADDR_EC_GIRQ20_ENABLE_CLEAR 0x4000C0FC
\r
1210 #define MMCR_EC_GIRQ20_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ20_ENABLE_CLEAR))
\r
1212 #define ADDR_EC_GIRQ21_SOURCE 0x4000C104
\r
1213 #define MMCR_EC_GIRQ21_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ21_SOURCE))
\r
1215 #define ADDR_EC_GIRQ21_ENABLE_SET 0x4000C108
\r
1216 #define MMCR_EC_GIRQ21_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_SET))
\r
1218 #define ADDR_EC_GIRQ21_RESULT 0x4000C10C
\r
1219 #define MMCR_EC_GIRQ21_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ21_RESULT))
\r
1221 #define ADDR_EC_GIRQ21_ENABLE_CLEAR 0x4000C110
\r
1222 #define MMCR_EC_GIRQ21_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ21_ENABLE_CLEAR))
\r
1224 #define ADDR_EC_GIRQ22_SOURCE 0x4000C118
\r
1225 #define MMCR_EC_GIRQ22_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ22_SOURCE))
\r
1227 #define ADDR_EC_GIRQ22_ENABLE_SET 0x4000C11C
\r
1228 #define MMCR_EC_GIRQ22_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_SET))
\r
1230 #define ADDR_EC_GIRQ22_RESULT 0x4000C120
\r
1231 #define MMCR_EC_GIRQ22_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ22_RESULT))
\r
1233 #define ADDR_EC_GIRQ22_ENABLE_CLEAR 0x4000C124
\r
1234 #define MMCR_EC_GIRQ22_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ22_ENABLE_CLEAR))
\r
1236 #define ADDR_EC_GIRQ23_SOURCE 0x4000C12C
\r
1237 #define MMCR_EC_GIRQ23_SOURCE (*(VUINT32 *)(ADDR_EC_GIRQ23_SOURCE))
\r
1239 #define ADDR_EC_GIRQ23_ENABLE_SET 0x4000C130
\r
1240 #define MMCR_EC_GIRQ23_ENABLE_SET (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_SET))
\r
1242 #define ADDR_EC_GIRQ23_RESULT 0x4000C134
\r
1243 #define MMCR_EC_GIRQ23_RESULT (*(VUINT32 *)(ADDR_EC_GIRQ23_RESULT))
\r
1245 #define ADDR_EC_GIRQ23_ENABLE_CLEAR 0x4000C138
\r
1246 #define MMCR_EC_GIRQ23_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_GIRQ23_ENABLE_CLEAR))
\r
1248 #define ADDR_EC_BLOCK_ENABLE_SET 0x4000C200
\r
1249 #define MMCR_EC_BLOCK_ENABLE_SET (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_SET))
\r
1251 #define ADDR_EC_BLOCK_ENABLE_CLEAR 0x4000C204
\r
1252 #define MMCR_EC_BLOCK_ENABLE_CLEAR (*(VUINT32 *)(ADDR_EC_BLOCK_ENABLE_CLEAR))
\r
1254 #define ADDR_EC_BLOCK_IRQ_VECTOR 0x4000C208
\r
1255 #define MMCR_EC_BLOCK_IRQ_VECTOR (*(VUINT32 *)(ADDR_EC_BLOCK_IRQ_VECTOR))
\r
1257 /***************************************************************
\r
1259 ***************************************************************/
\r
1260 #define ADDR_RPM_FAN_SETTING 0x4000A000
\r
1261 #define MMCR_RPM_FAN_SETTING (*(VUINT8 *)(ADDR_RPM_FAN_SETTING))
\r
1263 #define ADDR_RPM_PWM_DIVIDE 0x4000A001
\r
1264 #define MMCR_RPM_PWM_DIVIDE (*(VUINT8 *)(ADDR_RPM_PWM_DIVIDE))
\r
1266 #define ADDR_RPM_FAN_CONFIGURATION_1 0x4000A002
\r
1267 #define MMCR_RPM_FAN_CONFIGURATION_1 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_1))
\r
1269 #define ADDR_RPM_FAN_CONFIGURATION_2 0x4000A003
\r
1270 #define MMCR_RPM_FAN_CONFIGURATION_2 (*(VUINT8 *)(ADDR_RPM_FAN_CONFIGURATION_2))
\r
1272 #define ADDR_RPM_GAIN 0x4000A005
\r
1273 #define MMCR_RPM_GAIN (*(VUINT8 *)(ADDR_RPM_GAIN))
\r
1275 #define ADDR_RPM_FAN_SPIN_UP_CONFIGURATION 0x4000A006
\r
1276 #define MMCR_RPM_FAN_SPIN_UP_CONFIGURATION (*(VUINT8 *)(ADDR_RPM_FAN_SPIN_UP_CONFIGURATION))
\r
1278 #define ADDR_RPM_FAN_STEP 0x4000A007
\r
1279 #define MMCR_RPM_FAN_STEP (*(VUINT8 *)(ADDR_RPM_FAN_STEP))
\r
1281 #define ADDR_RPM_FAN_MINIMUM_DRIVE 0x4000A008
\r
1282 #define MMCR_RPM_FAN_MINIMUM_DRIVE (*(VUINT8 *)(ADDR_RPM_FAN_MINIMUM_DRIVE))
\r
1284 #define ADDR_RPM_VALID_TACH_COUNT 0x4000A009
\r
1285 #define MMCR_RPM_VALID_TACH_COUNT (*(VUINT8 *)(ADDR_RPM_VALID_TACH_COUNT))
\r
1287 #define ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE 0x4000A00A
\r
1288 #define MMCR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_LOW_BYTE))
\r
1290 #define ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE 0x4000A00B
\r
1291 #define MMCR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_FAN_DRIVE_FAIL_BAND_HIGH_BYTE))
\r
1293 #define ADDR_RPM_TACH_TARGET_LOW_BYTE 0x4000A00C
\r
1294 #define MMCR_RPM_TACH_TARGET_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_LOW_BYTE))
\r
1296 #define ADDR_RPM_TACH_TARGET_HIGH_BYTE 0x4000A00D
\r
1297 #define MMCR_RPM_TACH_TARGET_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_TARGET_HIGH_BYTE))
\r
1299 #define ADDR_RPM_TACH_READING_LOW_BYTE 0x4000A00E
\r
1300 #define MMCR_RPM_TACH_READING_LOW_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_LOW_BYTE))
\r
1302 #define ADDR_RPM_TACH_READING_HIGH_BYTE 0x4000A00F
\r
1303 #define MMCR_RPM_TACH_READING_HIGH_BYTE (*(VUINT8 *)(ADDR_RPM_TACH_READING_HIGH_BYTE))
\r
1305 #define ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY 0x4000A010
\r
1306 #define MMCR_RPM_PWM_DRIVER_BASE_FREQUENCY (*(VUINT8 *)(ADDR_RPM_PWM_DRIVER_BASE_FREQUENCY))
\r
1308 #define ADDR_RPM_FAN_STATUS 0x4000A011
\r
1309 #define MMCR_RPM_FAN_STATUS (*(VUINT8 *)(ADDR_RPM_FAN_STATUS))
\r
1311 #define ADDR_RPM_FAN_TEST 0x4000A014
\r
1312 #define MMCR_RPM_FAN_TEST (*(VUINT8 *)(ADDR_RPM_FAN_TEST))
\r
1314 #define ADDR_RPM_FAN_TEST1 0x4000A015
\r
1315 #define MMCR_RPM_FAN_TEST1 (*(VUINT8 *)(ADDR_RPM_FAN_TEST1))
\r
1317 #define ADDR_RPM_FAN_TEST2 0x4000A016
\r
1318 #define MMCR_RPM_FAN_TEST2 (*(VUINT8 *)(ADDR_RPM_FAN_TEST2))
\r
1320 #define ADDR_RPM_FAN_TEST3 0x4000A017
\r
1321 #define MMCR_RPM_FAN_TEST3 (*(VUINT8 *)(ADDR_RPM_FAN_TEST3))
\r
1323 /***************************************************************
\r
1324 * V2P (HP ckt#1) 32bit_aligned
\r
1325 ***************************************************************/
\r
1326 #define ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY 0x40007C80
\r
1327 #define MMCR_V2P_ADC2PWM_OUTPUT_FREQUENCY (*(VUINT32 *)(ADDR_V2P_ADC2PWM_OUTPUT_FREQUENCY))
\r
1329 #define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW 0x40007C84
\r
1330 #define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_LOW))
\r
1332 #define ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH 0x40007C88
\r
1333 #define MMCR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH (*(VUINT32 *)(ADDR_V2P_ADC2PWM_VOLTAGE_THRESHOLD_HIGH))
\r
1335 #define ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA 0x40007C8C
\r
1336 #define MMCR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_QUANTA))
\r
1338 #define ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS 0x40007C90
\r
1339 #define MMCR_V2P_ADC2PWM_DUTY_CYCLE_STATUS (*(VUINT32 *)(ADDR_V2P_ADC2PWM_DUTY_CYCLE_STATUS))
\r
1341 #define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 0x40007C94
\r
1342 #define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_1))
\r
1344 #define ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 0x40007C98
\r
1345 #define MMCR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2 (*(VUINT32 *)(ADDR_V2P_ADC2PWM_NOTIFICATION_LIMIT_2))
\r
1347 #define ADDR_V2P_ADC2PWM_CONTROL 0x40007C9C
\r
1348 #define MMCR_V2P_ADC2PWM_CONTROL (*(VUINT32 *)(ADDR_V2P_ADC2PWM_CONTROL))
\r
1350 #define ADDR_V2P_LPF_CUT_OFF_FREQUENCY 0x40007CA0
\r
1351 #define MMCR_V2P_LPF_CUT_OFF_FREQUENCY (*(VUINT32 *)(ADDR_V2P_LPF_CUT_OFF_FREQUENCY))
\r
1353 #define ADDR_V2P_TEST 0x40007CA4
\r
1354 #define MMCR_V2P_TEST (*(VUINT32 *)(ADDR_V2P_TEST))
\r
1356 #define ADDR_V2P_NOTICE_DATA 0x40007CA8
\r
1357 #define MMCR_V2P_NOTICE_DATA (*(VUINT32 *)(ADDR_V2P_NOTICE_DATA))
\r
1359 #define ADDR_V2P_TEST_DATA 0x40007CAC
\r
1360 #define MMCR_V2P_TEST_DATA (*(VUINT32 *)(ADDR_V2P_TEST_DATA))
\r
1362 #define ADDR_V2P_COUNTER_START 0x40007CB0
\r
1363 #define MMCR_V2P_COUNTER_START (*(VUINT32 *)(ADDR_V2P_COUNTER_START))
\r
1365 #define ADDR_V2P_HYSTERESIS 0x40007CB4
\r
1366 #define MMCR_V2P_HYSTERESIS (*(VUINT32 *)(ADDR_V2P_HYSTERESIS))
\r
1368 #define ADDR_V2P_BIAS 0x40007CB8
\r
1369 #define MMCR_V2P_BIAS (*(VUINT32 *)(ADDR_V2P_BIAS))
\r
1371 #define ADDR_V2P_INTERRUPT_CONTROL 0x40007CBC
\r
1372 #define MMCR_V2P_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_V2P_INTERRUPT_CONTROL))
\r
1374 /***************************************************************
\r
1375 * VBAT_REGS (1322)
\r
1376 ***************************************************************/
\r
1377 #define ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS 0x4000A400
\r
1378 #define MMCR_VBAT_POWER_FAIL_AND_RESET_STATUS (*(VUINT8 *)(ADDR_VBAT_POWER_FAIL_AND_RESET_STATUS))
\r
1380 #define ADDR_VBAT_CONTROL 0x4000A404
\r
1381 #define MMCR_VBAT_CONTROL (*(VUINT8 *)(ADDR_VBAT_CONTROL))
\r
1383 #define ADDR_VBAT_CLOCK_ENABLE 0x4000A408
\r
1384 #define MMCR_VBAT_CLOCK_ENABLE (*(VUINT8 *)(ADDR_VBAT_CLOCK_ENABLE))
\r
1386 /***************************************************************
\r
1387 * EC_REG_BANK (1322)
\r
1388 ***************************************************************/
\r
1389 #define ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS 0x4000FC04
\r
1390 #define MMCR_EC_REG_BANK_AHB_ERROR_ADDRESS (*(VUINT32 *)(ADDR_EC_REG_BANK_AHB_ERROR_ADDRESS))
\r
1392 #define ADDR_EC_REG_BANK_INPUT_MUX0 0x4000FC08
\r
1393 #define MMCR_EC_REG_BANK_INPUT_MUX0 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX0))
\r
1395 #define ADDR_EC_REG_BANK_INPUT_MUX1 0x4000FC0C
\r
1396 #define MMCR_EC_REG_BANK_INPUT_MUX1 (*(VUINT32 *)(ADDR_EC_REG_BANK_INPUT_MUX1))
\r
1398 #define ADDR_EC_REG_BANK_ID 0x4000FC10
\r
1399 #define MMCR_EC_REG_BANK_ID (*(VUINT8 *)(ADDR_EC_REG_BANK_ID))
\r
1401 #define ADDR_EC_REG_BANK_AHB_ERROR_CONTROL 0x4000FC14
\r
1402 #define MMCR_EC_REG_BANK_AHB_ERROR_CONTROL (*(VUINT8 *)(ADDR_EC_REG_BANK_AHB_ERROR_CONTROL))
\r
1404 #define ADDR_EC_REG_BANK_INTERRUPT_CONTROL 0x4000FC18
\r
1405 #define MMCR_EC_REG_BANK_INTERRUPT_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_INTERRUPT_CONTROL))
\r
1407 #define ADDR_EC_REG_BANK_ETM_TRACE 0x4000FC1C
\r
1408 #define MMCR_EC_REG_BANK_ETM_TRACE (*(VUINT32 *)(ADDR_EC_REG_BANK_ETM_TRACE))
\r
1410 #define ADDR_EC_REG_BANK_JTAG_ENABLE 0x4000FC20
\r
1411 #define MMCR_EC_REG_BANK_JTAG_ENABLE (*(VUINT32 *)(ADDR_EC_REG_BANK_JTAG_ENABLE))
\r
1413 #define ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK 0x4000FC24
\r
1414 #define MMCR_EC_REG_BANK_PRIVATE_KEY_LOCK (*(VUINT32 *)(ADDR_EC_REG_BANK_PRIVATE_KEY_LOCK))
\r
1416 #define ADDR_EC_REG_BANK_WDT_COUNT 0x4000FC28
\r
1417 #define MMCR_EC_REG_BANK_WDT_COUNT (*(VUINT32 *)(ADDR_EC_REG_BANK_WDT_COUNT))
\r
1419 #define ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL 0x4000FC2C
\r
1420 #define MMCR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL (*(VUINT32 *)(ADDR_EC_REG_BANK_AES_HASH_BYTE_SWAP_CONTROL))
\r
1422 #define ADDR_EC_REG_BANK_ADC_VREF_TRIM 0x4000FC30
\r
1423 #define MMCR_EC_REG_BANK_ADC_VREF_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_TRIM))
\r
1425 #define ADDR_EC_REG_BANK_REGULATOR_TRIM 0x4000FC34
\r
1426 #define MMCR_EC_REG_BANK_REGULATOR_TRIM (*(VUINT32 *)(ADDR_EC_REG_BANK_REGULATOR_TRIM))
\r
1428 #define ADDR_EC_REG_BANK_ADC_VREF_PD 0x4000FC38
\r
1429 #define MMCR_EC_REG_BANK_ADC_VREF_PD (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_VREF_PD))
\r
1431 #define ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST 0x4000FC3C
\r
1432 #define MMCR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST (*(VUINT32 *)(ADDR_EC_REG_BANK_ADC_COMP_BIAS_CURRENT_ADJUST))
\r
1434 #define ADDR_EC_REG_BANK_MISC_TRIM 0x4000FC40
\r
1435 #define MMCR_EC_REG_BANK_MISC_TRIM (*(VUINT8 *)(ADDR_EC_REG_BANK_MISC_TRIM))
\r
1437 /***************************************************************
\r
1439 ***************************************************************/
\r
1440 #define ADDR_PCR_CHIP_SLEEP_ENABLE 0x40080100
\r
1441 #define MMCR_PCR_CHIP_SLEEP_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_SLEEP_ENABLE))
\r
1443 #define ADDR_PCR_CHIP_CLOCK_REQUIRED 0x40080104
\r
1444 #define MMCR_PCR_CHIP_CLOCK_REQUIRED (*(VUINT32 *)(ADDR_PCR_CHIP_CLOCK_REQUIRED))
\r
1446 #define ADDR_PCR_EC_SLEEP_ENABLES 0x40080108
\r
1447 #define MMCR_PCR_EC_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLES))
\r
1449 #define ADDR_PCR_EC_CLOCK_REQUIRED_STATUS 0x4008010C
\r
1450 #define MMCR_PCR_EC_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_STATUS))
\r
1452 #define ADDR_PCR_HOST_SLEEP_ENABLES 0x40080110
\r
1453 #define MMCR_PCR_HOST_SLEEP_ENABLES (*(VUINT32 *)(ADDR_PCR_HOST_SLEEP_ENABLES))
\r
1455 #define ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS 0x40080114
\r
1456 #define MMCR_PCR_HOST_CLOCK_REQUIRED_STATUS (*(VUINT32 *)(ADDR_PCR_HOST_CLOCK_REQUIRED_STATUS))
\r
1458 #define ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 0x40080118
\r
1459 #define MMCR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0 (*(VUINT32 *)(ADDR_PCR_CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0))
\r
1461 #define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120
\r
1462 #define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
\r
1464 #define ADDR_PCR_EC_SLEEP_ENABLE_2 0x40080124
\r
1465 #define MMCR_PCR_EC_SLEEP_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_SLEEP_ENABLE_2))
\r
1467 #define ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS 0x40080128
\r
1468 #define MMCR_PCR_EC_CLOCK_REQUIRED_2_STATUS (*(VUINT32 *)(ADDR_PCR_EC_CLOCK_REQUIRED_2_STATUS))
\r
1470 #define ADDR_PCR_SLOW_CLOCK_CONTROL 0x4008012C
\r
1471 #define MMCR_PCR_SLOW_CLOCK_CONTROL (*(VUINT32 *)(ADDR_PCR_SLOW_CLOCK_CONTROL))
\r
1473 #define ADDR_PCR_OSCILLATOR_ID 0x40080130
\r
1474 #define MMCR_PCR_OSCILLATOR_ID (*(VUINT32 *)(ADDR_PCR_OSCILLATOR_ID))
\r
1476 #define ADDR_PCR_CHIP_RESET_ENABLE 0x40080138
\r
1477 #define MMCR_PCR_CHIP_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_CHIP_RESET_ENABLE))
\r
1479 #define ADDR_PCR_HOST_RESET_ENABLE 0x4008013C
\r
1480 #define MMCR_PCR_HOST_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_HOST_RESET_ENABLE))
\r
1482 #define ADDR_PCR_EC_RESET_ENABLE 0x40080140
\r
1483 #define MMCR_PCR_EC_RESET_ENABLE (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE))
\r
1485 #define ADDR_PCR_EC_RESET_ENABLE_2 0x40080144
\r
1486 #define MMCR_PCR_EC_RESET_ENABLE_2 (*(VUINT32 *)(ADDR_PCR_EC_RESET_ENABLE_2))
\r
1488 #define ADDR_PCR_CLOCK_RESET_CONTROL 0x40080148
\r
1489 #define MMCR_PCR_CLOCK_RESET_CONTROL (*(VUINT32 *)(ADDR_PCR_CLOCK_RESET_CONTROL))
\r
1491 /***************************************************************
\r
1492 * Public Key Crypto Engine
\r
1493 ***************************************************************/
\r
1494 #define ADDR_PUBLIC_PK_CONFIGREG 0x4000BD00
\r
1495 #define MMCR_PUBLIC_PK_CONFIGREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONFIGREG))
\r
1497 #define ADDR_PUBLIC_PK_COMMANDREG 0x4000BD04
\r
1498 #define MMCR_PUBLIC_PK_COMMANDREG (*(VUINT32 *)(ADDR_PUBLIC_PK_COMMANDREG))
\r
1500 #define ADDR_PUBLIC_PK_CONTROLREG 0x4000BD08
\r
1501 #define MMCR_PUBLIC_PK_CONTROLREG (*(VUINT32 *)(ADDR_PUBLIC_PK_CONTROLREG))
\r
1503 #define ADDR_PUBLIC_PK_STATUSREG 0x4000BD0C
\r
1504 #define MMCR_PUBLIC_PK_STATUSREG (*(VUINT32 *)(ADDR_PUBLIC_PK_STATUSREG))
\r
1506 #define ADDR_PUBLIC_PK_VERSIONREG 0x4000BD10
\r
1507 #define MMCR_PUBLIC_PK_VERSIONREG (*(VUINT32 *)(ADDR_PUBLIC_PK_VERSIONREG))
\r
1509 #define ADDR_PUBLIC_PK_LOADMICROCODEREG 0x4000BD14
\r
1510 #define MMCR_PUBLIC_PK_LOADMICROCODEREG (*(VUINT32 *)(ADDR_PUBLIC_PK_LOADMICROCODEREG))
\r
1512 /***************************************************************
\r
1513 * Non Deterministic Random Number Generator
\r
1514 ***************************************************************/
\r
1515 #define ADDR_NON_CONTROLREG 0x4000BE00
\r
1516 #define MMCR_NON_CONTROLREG (*(VUINT32 *)(ADDR_NON_CONTROLREG))
\r
1518 #define ADDR_NON_FIFOLEVELREG 0x4000BE04
\r
1519 #define MMCR_NON_FIFOLEVELREG (*(VUINT32 *)(ADDR_NON_FIFOLEVELREG))
\r
1521 #define ADDR_NON_VERSIONREG 0x4000BE08
\r
1522 #define MMCR_NON_VERSIONREG (*(VUINT32 *)(ADDR_NON_VERSIONREG))
\r
1524 /***************************************************************
\r
1526 ***************************************************************/
\r
1527 #define ADDR_RTC_SECONDS 0x400F2800
\r
1528 #define MMCR_RTC_SECONDS (*(VUINT8 *)(ADDR_RTC_SECONDS))
\r
1530 #define ADDR_RTC_SECONDS_ALARM 0x400F2801
\r
1531 #define MMCR_RTC_SECONDS_ALARM (*(VUINT8 *)(ADDR_RTC_SECONDS_ALARM))
\r
1533 #define ADDR_RTC_MINUTES 0x400F2802
\r
1534 #define MMCR_RTC_MINUTES (*(VUINT8 *)(ADDR_RTC_MINUTES))
\r
1536 #define ADDR_RTC_MINUTES_ALARM 0x400F2803
\r
1537 #define MMCR_RTC_MINUTES_ALARM (*(VUINT8 *)(ADDR_RTC_MINUTES_ALARM))
\r
1539 #define ADDR_RTC_HOURS 0x400F2804
\r
1540 #define MMCR_RTC_HOURS (*(VUINT8 *)(ADDR_RTC_HOURS))
\r
1542 #define ADDR_RTC_HOURS_ALARM 0x400F2805
\r
1543 #define MMCR_RTC_HOURS_ALARM (*(VUINT8 *)(ADDR_RTC_HOURS_ALARM))
\r
1545 #define ADDR_RTC_DAY_OF_WEEK 0x400F2806
\r
1546 #define MMCR_RTC_DAY_OF_WEEK (*(VUINT8 *)(ADDR_RTC_DAY_OF_WEEK))
\r
1548 #define ADDR_RTC_DAY_OF_MONTH 0x400F2807
\r
1549 #define MMCR_RTC_DAY_OF_MONTH (*(VUINT8 *)(ADDR_RTC_DAY_OF_MONTH))
\r
1551 #define ADDR_RTC_MONTH 0x400F2808
\r
1552 #define MMCR_RTC_MONTH (*(VUINT8 *)(ADDR_RTC_MONTH))
\r
1554 #define ADDR_RTC_YEAR 0x400F2809
\r
1555 #define MMCR_RTC_YEAR (*(VUINT8 *)(ADDR_RTC_YEAR))
\r
1557 #define ADDR_RTC_A 0x400F280A
\r
1558 #define MMCR_RTC_A (*(VUINT8 *)(ADDR_RTC_A))
\r
1560 #define ADDR_RTC_B 0x400F280B
\r
1561 #define MMCR_RTC_B (*(VUINT8 *)(ADDR_RTC_B))
\r
1563 #define ADDR_RTC_C 0x400F280C
\r
1564 #define MMCR_RTC_C (*(VUINT8 *)(ADDR_RTC_C))
\r
1566 #define ADDR_RTC_D 0x400F280D
\r
1567 #define MMCR_RTC_D (*(VUINT8 *)(ADDR_RTC_D))
\r
1569 #define ADDR_RTC_CONTROL 0x400F2810
\r
1570 #define MMCR_RTC_CONTROL (*(VUINT8 *)(ADDR_RTC_CONTROL))
\r
1572 #define ADDR_RTC_WEEK_ALARM 0x400F2814
\r
1573 #define MMCR_RTC_WEEK_ALARM (*(VUINT8 *)(ADDR_RTC_WEEK_ALARM))
\r
1575 #define ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD 0x400F2818
\r
1576 #define MMCR_RTC_DAYLIGHT_SAVINGS_FORWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_FORWARD))
\r
1578 #define ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD 0x400F281C
\r
1579 #define MMCR_RTC_DAYLIGHT_SAVINGS_BACKWARD (*(VUINT32 *)(ADDR_RTC_DAYLIGHT_SAVINGS_BACKWARD))
\r
1581 #define ADDR_RTC_TEST_MODE 0x400F2820
\r
1582 #define MMCR_RTC_TEST_MODE (*(VUINT8 *)(ADDR_RTC_TEST_MODE))
\r
1584 /***************************************************************
\r
1585 * Analog to Digital Converter (ADC)
\r
1586 ***************************************************************/
\r
1587 #define ADDR_ADC_CONTROL 0x40007C00
\r
1588 #define MMCR_ADC_CONTROL (*(VUINT32 *)(ADDR_ADC_CONTROL))
\r
1590 #define ADDR_ADC_DELAY 0x40007C04
\r
1591 #define MMCR_ADC_DELAY (*(VUINT32 *)(ADDR_ADC_DELAY))
\r
1593 #define ADDR_ADC_STATUS 0x40007C08
\r
1594 #define MMCR_ADC_STATUS (*(VUINT32 *)(ADDR_ADC_STATUS))
\r
1596 #define ADDR_ADC_SINGLE 0x40007C0C
\r
1597 #define MMCR_ADC_SINGLE (*(VUINT32 *)(ADDR_ADC_SINGLE))
\r
1599 #define ADDR_ADC_REPEAT 0x40007C10
\r
1600 #define MMCR_ADC_REPEAT (*(VUINT32 *)(ADDR_ADC_REPEAT))
\r
1602 #define ADDR_ADC_CHANNEL_0_READINGS 0x40007C14
\r
1603 #define MMCR_ADC_CHANNEL_0_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_0_READINGS))
\r
1605 #define ADDR_ADC_CHANNEL_1_READINGS 0x40007C18
\r
1606 #define MMCR_ADC_CHANNEL_1_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_1_READINGS))
\r
1608 #define ADDR_ADC_CHANNEL_2_READINGS 0x40007C1C
\r
1609 #define MMCR_ADC_CHANNEL_2_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_2_READINGS))
\r
1611 #define ADDR_ADC_CHANNEL_3_READINGS 0x40007C20
\r
1612 #define MMCR_ADC_CHANNEL_3_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_3_READINGS))
\r
1614 #define ADDR_ADC_CHANNEL_4_READINGS 0x40007C24
\r
1615 #define MMCR_ADC_CHANNEL_4_READINGS (*(VUINT32 *)(ADDR_ADC_CHANNEL_4_READINGS))
\r
1617 #define ADDR_ADC_DEBUG_FPGA_TEST_MODE 0x40007C54
\r
1618 #define MMCR_ADC_DEBUG_FPGA_TEST_MODE (*(VUINT32 *)(ADDR_ADC_DEBUG_FPGA_TEST_MODE))
\r
1620 #define ADDR_ADC_TEST 0x40007C78
\r
1621 #define MMCR_ADC_TEST (*(VUINT32 *)(ADDR_ADC_TEST))
\r
1623 #define ADDR_ADC_CONFIGURATION 0x40007C7C
\r
1624 #define MMCR_ADC_CONFIGURATION (*(VUINT32 *)(ADDR_ADC_CONFIGURATION))
\r
1626 /***************************************************************
\r
1628 ***************************************************************/
\r
1629 #define ADDR_EFUSE_CONTROL 0x40082000
\r
1630 #define MMCR_EFUSE_CONTROL (*(VUINT8 *)(ADDR_EFUSE_CONTROL))
\r
1632 #define ADDR_EFUSE_MANUAL_CONTROL 0x40082004
\r
1633 #define MMCR_EFUSE_MANUAL_CONTROL (*(VUINT8 *)(ADDR_EFUSE_MANUAL_CONTROL))
\r
1635 #define ADDR_EFUSE_MANUAL_MODE_ADDRESS 0x40082006
\r
1636 #define MMCR_EFUSE_MANUAL_MODE_ADDRESS (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_ADDRESS))
\r
1638 #define ADDR_EFUSE_MANUAL_MODE_DATA 0x4008200C
\r
1639 #define MMCR_EFUSE_MANUAL_MODE_DATA (*(VUINT16 *)(ADDR_EFUSE_MANUAL_MODE_DATA))
\r
1641 /***************************************************************
\r
1642 * AES Crypto Engine & Hash Function
\r
1643 ***************************************************************/
\r
1644 #define ADDR_AES_CONFIGREG 0x4000D200
\r
1645 #define MMCR_AES_CONFIGREG (*(VUINT32 *)(ADDR_AES_CONFIGREG))
\r
1647 #define ADDR_AES_COMMANDREG 0x4000D204
\r
1648 #define MMCR_AES_COMMANDREG (*(VUINT32 *)(ADDR_AES_COMMANDREG))
\r
1650 #define ADDR_AES_CONTROLREG 0x4000D208
\r
1651 #define MMCR_AES_CONTROLREG (*(VUINT32 *)(ADDR_AES_CONTROLREG))
\r
1653 #define ADDR_AES_STATUSREG 0x4000D20C
\r
1654 #define MMCR_AES_STATUSREG (*(VUINT32 *)(ADDR_AES_STATUSREG))
\r
1656 #define ADDR_AES_VERSIONREG 0x4000D210
\r
1657 #define MMCR_AES_VERSIONREG (*(VUINT32 *)(ADDR_AES_VERSIONREG))
\r
1659 #define ADDR_AES_NBHEADERREG 0x4000D214
\r
1660 #define MMCR_AES_NBHEADERREG (*(VUINT32 *)(ADDR_AES_NBHEADERREG))
\r
1662 #define ADDR_AES_LASTHEADERREG 0x4000D218
\r
1663 #define MMCR_AES_LASTHEADERREG (*(VUINT32 *)(ADDR_AES_LASTHEADERREG))
\r
1665 #define ADDR_AES_NBBLOCKREG 0x4000D21C
\r
1666 #define MMCR_AES_NBBLOCKREG (*(VUINT32 *)(ADDR_AES_NBBLOCKREG))
\r
1668 #define ADDR_AES_LASTBLOCKREG 0x4000D220
\r
1669 #define MMCR_AES_LASTBLOCKREG (*(VUINT32 *)(ADDR_AES_LASTBLOCKREG))
\r
1671 #define ADDR_AES_DMAINREG 0x4000D224
\r
1672 #define MMCR_AES_DMAINREG (*(VUINT32 *)(ADDR_AES_DMAINREG))
\r
1674 #define ADDR_AES_DMAOUTREG 0x4000D228
\r
1675 #define MMCR_AES_DMAOUTREG (*(VUINT32 *)(ADDR_AES_DMAOUTREG))
\r
1677 #define ADDR_AES_SHAMODE_REGISTER 0x4000D000
\r
1678 #define MMCR_AES_SHAMODE_REGISTER (*(VUINT32 *)(ADDR_AES_SHAMODE_REGISTER))
\r
1680 #define ADDR_AES_NBBLOCK_REGISTER 0x4000D004
\r
1681 #define MMCR_AES_NBBLOCK_REGISTER (*(VUINT32 *)(ADDR_AES_NBBLOCK_REGISTER))
\r
1683 #define ADDR_AES_CONTROL 0x4000D008
\r
1684 #define MMCR_AES_CONTROL (*(VUINT32 *)(ADDR_AES_CONTROL))
\r
1686 #define ADDR_AES_STATUS 0x4000D00C
\r
1687 #define MMCR_AES_STATUS (*(VUINT32 *)(ADDR_AES_STATUS))
\r
1689 #define ADDR_AES_VERSION 0x4000D010
\r
1690 #define MMCR_AES_VERSION (*(VUINT32 *)(ADDR_AES_VERSION))
\r
1692 #define ADDR_AES_GENERICVALUE_REGISTER 0x4000D014
\r
1693 #define MMCR_AES_GENERICVALUE_REGISTER (*(VUINT32 *)(ADDR_AES_GENERICVALUE_REGISTER))
\r
1695 #define ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS 0x4000D018
\r
1696 #define MMCR_AES_INITIAL_HASH_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_INITIAL_HASH_SOURCE_ADDRESS))
\r
1698 #define ADDR_AES_DATA_SOURCE_ADDRESS 0x4000D01C
\r
1699 #define MMCR_AES_DATA_SOURCE_ADDRESS (*(VUINT32 *)(ADDR_AES_DATA_SOURCE_ADDRESS))
\r
1701 #define ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS 0x4000D020
\r
1702 #define MMCR_AES_HASH_RESULT_DESTINATION_ADDRESS (*(VUINT32 *)(ADDR_AES_HASH_RESULT_DESTINATION_ADDRESS))
\r
1704 /***************************************************************
\r
1706 ***************************************************************/
\r
1707 #define ADDR_LPC_ACTIVATE 0x400F3330
\r
1708 #define MMCR_LPC_ACTIVATE (*(VUINT8 *)(ADDR_LPC_ACTIVATE))
\r
1710 #define ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION 0x400F3340
\r
1711 #define MMCR_LPC_SIRQ0_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ0_INTERRUPT_CONFIGURATION))
\r
1713 #define ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION 0x400F3341
\r
1714 #define MMCR_LPC_SIRQ1_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ1_INTERRUPT_CONFIGURATION))
\r
1716 #define ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION 0x400F3342
\r
1717 #define MMCR_LPC_SIRQ2_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ2_INTERRUPT_CONFIGURATION))
\r
1719 #define ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION 0x400F3343
\r
1720 #define MMCR_LPC_SIRQ3_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ3_INTERRUPT_CONFIGURATION))
\r
1722 #define ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION 0x400F3344
\r
1723 #define MMCR_LPC_SIRQ4_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ4_INTERRUPT_CONFIGURATION))
\r
1725 #define ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION 0x400F3345
\r
1726 #define MMCR_LPC_SIRQ5_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ5_INTERRUPT_CONFIGURATION))
\r
1728 #define ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION 0x400F3346
\r
1729 #define MMCR_LPC_SIRQ6_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ6_INTERRUPT_CONFIGURATION))
\r
1731 #define ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION 0x400F3347
\r
1732 #define MMCR_LPC_SIRQ7_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ7_INTERRUPT_CONFIGURATION))
\r
1734 #define ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION 0x400F3348
\r
1735 #define MMCR_LPC_SIRQ8_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ8_INTERRUPT_CONFIGURATION))
\r
1737 #define ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION 0x400F3349
\r
1738 #define MMCR_LPC_SIRQ9_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ9_INTERRUPT_CONFIGURATION))
\r
1740 #define ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION 0x400F334A
\r
1741 #define MMCR_LPC_SIRQ10_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ10_INTERRUPT_CONFIGURATION))
\r
1743 #define ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION 0x400F334B
\r
1744 #define MMCR_LPC_SIRQ11_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ11_INTERRUPT_CONFIGURATION))
\r
1746 #define ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION 0x400F334C
\r
1747 #define MMCR_LPC_SIRQ12_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ12_INTERRUPT_CONFIGURATION))
\r
1749 #define ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION 0x400F334D
\r
1750 #define MMCR_LPC_SIRQ13_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ13_INTERRUPT_CONFIGURATION))
\r
1752 #define ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION 0x400F334E
\r
1753 #define MMCR_LPC_SIRQ14_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ14_INTERRUPT_CONFIGURATION))
\r
1755 #define ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION 0x400F334F
\r
1756 #define MMCR_LPC_SIRQ15_INTERRUPT_CONFIGURATION (*(VUINT8 *)(ADDR_LPC_SIRQ15_INTERRUPT_CONFIGURATION))
\r
1758 #define ADDR_LPC_INTERFACE_BAR 0x400F3360
\r
1759 #define MMCR_LPC_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_INTERFACE_BAR))
\r
1761 #define ADDR_LPC_EM_INTERFACE_0_BAR 0x400F3364
\r
1762 #define MMCR_LPC_EM_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_EM_INTERFACE_0_BAR))
\r
1764 #define ADDR_LPC_UART_0_BAR 0x400F3368
\r
1765 #define MMCR_LPC_UART_0_BAR (*(VUINT32 *)(ADDR_LPC_UART_0_BAR))
\r
1767 #define ADDR_LPC_KEYBOARD_CONTROLLER_BAR 0x400F3378
\r
1768 #define MMCR_LPC_KEYBOARD_CONTROLLER_BAR (*(VUINT32 *)(ADDR_LPC_KEYBOARD_CONTROLLER_BAR))
\r
1770 #define ADDR_LPC_ACPI_EC_INTERFACE_0_BAR 0x400F3388
\r
1771 #define MMCR_LPC_ACPI_EC_INTERFACE_0_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_0_BAR))
\r
1773 #define ADDR_LPC_ACPI_EC_INTERFACE_1_BAR 0x400F338C
\r
1774 #define MMCR_LPC_ACPI_EC_INTERFACE_1_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_EC_INTERFACE_1_BAR))
\r
1776 #define ADDR_LPC_ACPI_PM1_INTERFACE_BAR 0x400F3390
\r
1777 #define MMCR_LPC_ACPI_PM1_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_ACPI_PM1_INTERFACE_BAR))
\r
1779 #define ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR 0x400F3394
\r
1780 #define MMCR_LPC_LEGACY_GATEA20_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_LEGACY_GATEA20_INTERFACE_BAR))
\r
1782 #define ADDR_LPC_MAILBOXS_INTERFACE_BAR 0x400F3398
\r
1783 #define MMCR_LPC_MAILBOXS_INTERFACE_BAR (*(VUINT32 *)(ADDR_LPC_MAILBOXS_INTERFACE_BAR))
\r
1785 #define ADDR_LPC_BUS_MONITOR 0x400F3104
\r
1786 #define MMCR_LPC_BUS_MONITOR (*(VUINT32 *)(ADDR_LPC_BUS_MONITOR))
\r
1788 #define ADDR_LPC_HOST_BUS_ERROR 0x400F3108
\r
1789 #define MMCR_LPC_HOST_BUS_ERROR (*(VUINT32 *)(ADDR_LPC_HOST_BUS_ERROR))
\r
1791 #define ADDR_LPC_EC_SERIRQ 0x400F310C
\r
1792 #define MMCR_LPC_EC_SERIRQ (*(VUINT32 *)(ADDR_LPC_EC_SERIRQ))
\r
1794 #define ADDR_LPC_EC_CLOCK_CONTROL 0x400F3110
\r
1795 #define MMCR_LPC_EC_CLOCK_CONTROL (*(VUINT32 *)(ADDR_LPC_EC_CLOCK_CONTROL))
\r
1797 #define ADDR_LPC_BAR_INHIBIT 0x400F3120
\r
1798 #define MMCR_LPC_BAR_INHIBIT (*(VUINT32 *)(ADDR_LPC_BAR_INHIBIT))
\r
1800 #define ADDR_LPC_BAR_INIT 0x400F3130
\r
1801 #define MMCR_LPC_BAR_INIT (*(VUINT16 *)(ADDR_LPC_BAR_INIT))
\r
1803 #define ADDR_LPC_MEMORY_HOST_CONFIGURATION 0x400F31FC
\r
1804 #define MMCR_LPC_MEMORY_HOST_CONFIGURATION (*(VUINT32 *)(ADDR_LPC_MEMORY_HOST_CONFIGURATION))
\r
1806 /***************************************************************
\r
1808 ***************************************************************/
\r
1809 #define ADDR_GPIO000_PIN_CONTROL 0x40081000
\r
1810 #define MMCR_GPIO000_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL))
\r
1812 #define ADDR_GPIO001_PIN_CONTROL 0x40081004
\r
1813 #define MMCR_GPIO001_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL))
\r
1815 #define ADDR_GPIO002_PIN_CONTROL 0x40081008
\r
1816 #define MMCR_GPIO002_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL))
\r
1818 #define ADDR_GPIO003_PIN_CONTROL 0x4008100C
\r
1819 #define MMCR_GPIO003_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL))
\r
1821 #define ADDR_GPIO004_PIN_CONTROL 0x40081010
\r
1822 #define MMCR_GPIO004_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL))
\r
1824 #define ADDR_GPIO005_PIN_CONTROL 0x40081014
\r
1825 #define MMCR_GPIO005_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL))
\r
1827 #define ADDR_GPIO006_PIN_CONTROL 0x40081018
\r
1828 #define MMCR_GPIO006_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL))
\r
1830 #define ADDR_GPIO007_PIN_CONTROL 0x4008101C
\r
1831 #define MMCR_GPIO007_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL))
\r
1833 #define ADDR_GPIO010_PIN_CONTROL 0x40081020
\r
1834 #define MMCR_GPIO010_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL))
\r
1836 #define ADDR_GPIO011_PIN_CONTROL 0x40081024
\r
1837 #define MMCR_GPIO011_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL))
\r
1839 #define ADDR_GPIO012_PIN_CONTROL 0x40081028
\r
1840 #define MMCR_GPIO012_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL))
\r
1842 #define ADDR_GPIO013_PIN_CONTROL 0x4008102C
\r
1843 #define MMCR_GPIO013_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL))
\r
1845 #define ADDR_GPIO014_PIN_CONTROL 0x40081030
\r
1846 #define MMCR_GPIO014_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL))
\r
1848 #define ADDR_GPIO015_PIN_CONTROL 0x40081034
\r
1849 #define MMCR_GPIO015_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL))
\r
1851 #define ADDR_GPIO016_PIN_CONTROL 0x40081038
\r
1852 #define MMCR_GPIO016_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL))
\r
1854 #define ADDR_GPIO017_PIN_CONTROL 0x4008103C
\r
1855 #define MMCR_GPIO017_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL))
\r
1857 #define ADDR_GPIO020_PIN_CONTROL 0x40081040
\r
1858 #define MMCR_GPIO020_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL))
\r
1860 #define ADDR_GPIO021_PIN_CONTROL 0x40081044
\r
1861 #define MMCR_GPIO021_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL))
\r
1863 #define ADDR_GPIO022_PIN_CONTROL 0x40081048
\r
1864 #define MMCR_GPIO022_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL))
\r
1866 #define ADDR_GPIO023_PIN_CONTROL 0x4008104C
\r
1867 #define MMCR_GPIO023_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL))
\r
1869 #define ADDR_GPIO024_PIN_CONTROL 0x40081050
\r
1870 #define MMCR_GPIO024_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL))
\r
1872 #define ADDR_GPIO025_PIN_CONTROL 0x40081054
\r
1873 #define MMCR_GPIO025_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL))
\r
1875 #define ADDR_GPIO026_PIN_CONTROL 0x40081058
\r
1876 #define MMCR_GPIO026_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL))
\r
1878 #define ADDR_GPIO027_PIN_CONTROL 0x4008105C
\r
1879 #define MMCR_GPIO027_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL))
\r
1881 #define ADDR_GPIO030_PIN_CONTROL 0x40081060
\r
1882 #define MMCR_GPIO030_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL))
\r
1884 #define ADDR_GPIO031_PIN_CONTROL 0x40081064
\r
1885 #define MMCR_GPIO031_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL))
\r
1887 #define ADDR_GPIO032_PIN_CONTROL 0x40081068
\r
1888 #define MMCR_GPIO032_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL))
\r
1890 #define ADDR_GPIO033_PIN_CONTROL 0x4008106C
\r
1891 #define MMCR_GPIO033_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL))
\r
1893 #define ADDR_GPIO034_PIN_CONTROL 0x40081070
\r
1894 #define MMCR_GPIO034_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL))
\r
1896 #define ADDR_GPIO035_PIN_CONTROL 0x40081074
\r
1897 #define MMCR_GPIO035_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL))
\r
1899 #define ADDR_GPIO036_PIN_CONTROL 0x40081078
\r
1900 #define MMCR_GPIO036_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL))
\r
1902 #define ADDR_GPIO040_PIN_CONTROL 0x40081080
\r
1903 #define MMCR_GPIO040_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL))
\r
1905 #define ADDR_GPIO041_PIN_CONTROL 0x40081084
\r
1906 #define MMCR_GPIO041_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL))
\r
1908 #define ADDR_GPIO042_PIN_CONTROL 0x40081088
\r
1909 #define MMCR_GPIO042_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL))
\r
1911 #define ADDR_GPIO043_PIN_CONTROL 0x4008108C
\r
1912 #define MMCR_GPIO043_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL))
\r
1914 #define ADDR_GPIO044_PIN_CONTROL 0x40081090
\r
1915 #define MMCR_GPIO044_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL))
\r
1917 #define ADDR_GPIO045_PIN_CONTROL 0x40081094
\r
1918 #define MMCR_GPIO045_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL))
\r
1920 #define ADDR_GPIO046_PIN_CONTROL 0x40081098
\r
1921 #define MMCR_GPIO046_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL))
\r
1923 #define ADDR_GPIO047_PIN_CONTROL 0x4008109C
\r
1924 #define MMCR_GPIO047_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL))
\r
1926 #define ADDR_GPIO050_PIN_CONTROL 0x400810A0
\r
1927 #define MMCR_GPIO050_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL))
\r
1929 #define ADDR_GPIO051_PIN_CONTROL 0x400810A4
\r
1930 #define MMCR_GPIO051_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL))
\r
1932 #define ADDR_GPIO052_PIN_CONTROL 0x400810A8
\r
1933 #define MMCR_GPIO052_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL))
\r
1935 #define ADDR_GPIO053_PIN_CONTROL 0x400810AC
\r
1936 #define MMCR_GPIO053_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL))
\r
1938 #define ADDR_GPIO054_PIN_CONTROL 0x400810B0
\r
1939 #define MMCR_GPIO054_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL))
\r
1941 #define ADDR_GPIO055_PIN_CONTROL 0x400810B4
\r
1942 #define MMCR_GPIO055_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL))
\r
1944 #define ADDR_GPIO056_PIN_CONTROL 0x400810B8
\r
1945 #define MMCR_GPIO056_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL))
\r
1947 #define ADDR_GPIO057_PIN_CONTROL 0x400810BC
\r
1948 #define MMCR_GPIO057_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL))
\r
1950 #define ADDR_GPIO060_PIN_CONTROL 0x400810C0
\r
1951 #define MMCR_GPIO060_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL))
\r
1953 #define ADDR_GPIO061_PIN_CONTROL 0x400810C4
\r
1954 #define MMCR_GPIO061_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL))
\r
1956 #define ADDR_GPIO062_PIN_CONTROL 0x400810C8
\r
1957 #define MMCR_GPIO062_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL))
\r
1959 #define ADDR_GPIO063_PIN_CONTROL 0x400810CC
\r
1960 #define MMCR_GPIO063_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL))
\r
1962 #define ADDR_GPIO064_PIN_CONTROL 0x400810D0
\r
1963 #define MMCR_GPIO064_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL))
\r
1965 #define ADDR_GPIO065_PIN_CONTROL 0x400810D4
\r
1966 #define MMCR_GPIO065_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL))
\r
1968 #define ADDR_GPIO066_PIN_CONTROL 0x400810D8
\r
1969 #define MMCR_GPIO066_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL))
\r
1971 #define ADDR_GPIO067_PIN_CONTROL 0x400810DC
\r
1972 #define MMCR_GPIO067_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL))
\r
1974 #define ADDR_GPIO100_PIN_CONTROL 0x40081100
\r
1975 #define MMCR_GPIO100_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL))
\r
1977 #define ADDR_GPIO101_PIN_CONTROL 0x40081104
\r
1978 #define MMCR_GPIO101_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL))
\r
1980 #define ADDR_GPIO102_PIN_CONTROL 0x40081108
\r
1981 #define MMCR_GPIO102_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL))
\r
1983 #define ADDR_GPIO103_PIN_CONTROL 0x4008110C
\r
1984 #define MMCR_GPIO103_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL))
\r
1986 #define ADDR_GPIO104_PIN_CONTROL 0x40081110
\r
1987 #define MMCR_GPIO104_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL))
\r
1989 #define ADDR_GPIO105_PIN_CONTROL 0x40081114
\r
1990 #define MMCR_GPIO105_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL))
\r
1992 #define ADDR_GPIO106_PIN_CONTROL 0x40081118
\r
1993 #define MMCR_GPIO106_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL))
\r
1995 #define ADDR_GPIO107_PIN_CONTROL 0x4008111C
\r
1996 #define MMCR_GPIO107_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL))
\r
1998 #define ADDR_GPIO110_PIN_CONTROL 0x40081120
\r
1999 #define MMCR_GPIO110_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL))
\r
2001 #define ADDR_GPIO111_PIN_CONTROL 0x40081124
\r
2002 #define MMCR_GPIO111_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL))
\r
2004 #define ADDR_GPIO112_PIN_CONTROL 0x40081128
\r
2005 #define MMCR_GPIO112_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL))
\r
2007 #define ADDR_GPIO113_PIN_CONTROL 0x4008112C
\r
2008 #define MMCR_GPIO113_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL))
\r
2010 #define ADDR_GPIO114_PIN_CONTROL 0x40081130
\r
2011 #define MMCR_GPIO114_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL))
\r
2013 #define ADDR_GPIO115_PIN_CONTROL 0x40081134
\r
2014 #define MMCR_GPIO115_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL))
\r
2016 #define ADDR_GPIO116_PIN_CONTROL 0x40081138
\r
2017 #define MMCR_GPIO116_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL))
\r
2019 #define ADDR_GPIO117_PIN_CONTROL 0x4008113C
\r
2020 #define MMCR_GPIO117_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL))
\r
2022 #define ADDR_GPIO120_PIN_CONTROL 0x40081140
\r
2023 #define MMCR_GPIO120_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL))
\r
2025 #define ADDR_GPIO121_PIN_CONTROL 0x40081144
\r
2026 #define MMCR_GPIO121_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL))
\r
2028 #define ADDR_GPIO122_PIN_CONTROL 0x40081148
\r
2029 #define MMCR_GPIO122_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL))
\r
2031 #define ADDR_GPIO123_PIN_CONTROL 0x4008114C
\r
2032 #define MMCR_GPIO123_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL))
\r
2034 #define ADDR_GPIO124_PIN_CONTROL 0x40081150
\r
2035 #define MMCR_GPIO124_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL))
\r
2037 #define ADDR_GPIO125_PIN_CONTROL 0x40081154
\r
2038 #define MMCR_GPIO125_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL))
\r
2040 #define ADDR_GPIO126_PIN_CONTROL 0x40081158
\r
2041 #define MMCR_GPIO126_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL))
\r
2043 #define ADDR_GPIO127_PIN_CONTROL 0x4008115C
\r
2044 #define MMCR_GPIO127_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL))
\r
2046 #define ADDR_GPIO130_PIN_CONTROL 0x40081160
\r
2047 #define MMCR_GPIO130_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL))
\r
2049 #define ADDR_GPIO131_PIN_CONTROL 0x40081164
\r
2050 #define MMCR_GPIO131_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL))
\r
2052 #define ADDR_GPIO132_PIN_CONTROL 0x40081168
\r
2053 #define MMCR_GPIO132_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL))
\r
2055 #define ADDR_GPIO133_PIN_CONTROL 0x4008116C
\r
2056 #define MMCR_GPIO133_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL))
\r
2058 #define ADDR_GPIO134_PIN_CONTROL 0x40081170
\r
2059 #define MMCR_GPIO134_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL))
\r
2061 #define ADDR_GPIO135_PIN_CONTROL 0x40081174
\r
2062 #define MMCR_GPIO135_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL))
\r
2064 #define ADDR_GPIO136_PIN_CONTROL 0x40081178
\r
2065 #define MMCR_GPIO136_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL))
\r
2067 #define ADDR_GPIO140_PIN_CONTROL 0x40081180
\r
2068 #define MMCR_GPIO140_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL))
\r
2070 #define ADDR_GPIO141_PIN_CONTROL 0x40081184
\r
2071 #define MMCR_GPIO141_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL))
\r
2073 #define ADDR_GPIO142_PIN_CONTROL 0x40081188
\r
2074 #define MMCR_GPIO142_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL))
\r
2076 #define ADDR_GPIO143_PIN_CONTROL 0x4008118C
\r
2077 #define MMCR_GPIO143_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL))
\r
2079 #define ADDR_GPIO144_PIN_CONTROL 0x40081190
\r
2080 #define MMCR_GPIO144_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL))
\r
2082 #define ADDR_GPIO145_PIN_CONTROL 0x40081194
\r
2083 #define MMCR_GPIO145_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL))
\r
2085 #define ADDR_GPIO146_PIN_CONTROL 0x40081198
\r
2086 #define MMCR_GPIO146_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL))
\r
2088 #define ADDR_GPIO147_PIN_CONTROL 0x4008119C
\r
2089 #define MMCR_GPIO147_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL))
\r
2091 #define ADDR_GPIO150_PIN_CONTROL 0x400811A0
\r
2092 #define MMCR_GPIO150_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL))
\r
2094 #define ADDR_GPIO151_PIN_CONTROL 0x400811A4
\r
2095 #define MMCR_GPIO151_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL))
\r
2097 #define ADDR_GPIO152_PIN_CONTROL 0x400811A8
\r
2098 #define MMCR_GPIO152_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL))
\r
2100 #define ADDR_GPIO153_PIN_CONTROL 0x400811AC
\r
2101 #define MMCR_GPIO153_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL))
\r
2103 #define ADDR_GPIO154_PIN_CONTROL 0x400811B0
\r
2104 #define MMCR_GPIO154_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL))
\r
2106 #define ADDR_GPIO155_PIN_CONTROL 0x400811B4
\r
2107 #define MMCR_GPIO155_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL))
\r
2109 #define ADDR_GPIO156_PIN_CONTROL 0x400811B8
\r
2110 #define MMCR_GPIO156_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL))
\r
2112 #define ADDR_GPIO157_PIN_CONTROL 0x400811BC
\r
2113 #define MMCR_GPIO157_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL))
\r
2115 #define ADDR_GPIO160_PIN_CONTROL 0x400811C0
\r
2116 #define MMCR_GPIO160_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL))
\r
2118 #define ADDR_GPIO161_PIN_CONTROL 0x400811C4
\r
2119 #define MMCR_GPIO161_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL))
\r
2121 #define ADDR_GPIO162_PIN_CONTROL 0x400811C8
\r
2122 #define MMCR_GPIO162_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL))
\r
2124 #define ADDR_GPIO163_PIN_CONTROL 0x400811CC
\r
2125 #define MMCR_GPIO163_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL))
\r
2127 #define ADDR_GPIO164_PIN_CONTROL 0x400811D0
\r
2128 #define MMCR_GPIO164_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL))
\r
2130 #define ADDR_GPIO165_PIN_CONTROL 0x400811D4
\r
2131 #define MMCR_GPIO165_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL))
\r
2133 #define ADDR_GPIO200_PIN_CONTROL 0x40081200
\r
2134 #define MMCR_GPIO200_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL))
\r
2136 #define ADDR_GPIO201_PIN_CONTROL 0x40081204
\r
2137 #define MMCR_GPIO201_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL))
\r
2139 #define ADDR_GPIO202_PIN_CONTROL 0x40081208
\r
2140 #define MMCR_GPIO202_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL))
\r
2142 #define ADDR_GPIO203_PIN_CONTROL 0x4008120C
\r
2143 #define MMCR_GPIO203_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL))
\r
2145 #define ADDR_GPIO204_PIN_CONTROL 0x40081210
\r
2146 #define MMCR_GPIO204_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL))
\r
2148 #define ADDR_GPIO206_PIN_CONTROL 0x40081218
\r
2149 #define MMCR_GPIO206_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL))
\r
2151 #define ADDR_GPIO210_PIN_CONTROL 0x40081220
\r
2152 #define MMCR_GPIO210_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL))
\r
2154 #define ADDR_GPIO211_PIN_CONTROL 0x40081224
\r
2155 #define MMCR_GPIO211_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL))
\r
2157 #define ADDR_GPIO212_PIN_CONTROL 0x40081228
\r
2158 #define MMCR_GPIO212_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL))
\r
2160 #define ADDR_GPIO213_PIN_CONTROL 0x4008122C
\r
2161 #define MMCR_GPIO213_PIN_CONTROL (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL))
\r
2163 #define ADDR_GPIO_OUTPUT_GPIO_000_036 0x40081280
\r
2164 #define MMCR_GPIO_OUTPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_000_036))
\r
2166 #define ADDR_GPIO_OUTPUT_GPIO_040_076 0x40081284
\r
2167 #define MMCR_GPIO_OUTPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_040_076))
\r
2169 #define ADDR_GPIO_OUTPUT_GPIO_100_136 0x40081288
\r
2170 #define MMCR_GPIO_OUTPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_100_136))
\r
2172 #define ADDR_GPIO_OUTPUT_GPIO_140_176 0x4008128C
\r
2173 #define MMCR_GPIO_OUTPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_140_176))
\r
2175 #define ADDR_GPIO_OUTPUT_GPIO_200_236 0x40081290
\r
2176 #define MMCR_GPIO_OUTPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_OUTPUT_GPIO_200_236))
\r
2178 #define ADDR_GPIO_INPUT_GPIO_000_036 0x40081300
\r
2179 #define MMCR_GPIO_INPUT_GPIO_000_036 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_000_036))
\r
2181 #define ADDR_GPIO_INPUT_GPIO_040_076 0x40081304
\r
2182 #define MMCR_GPIO_INPUT_GPIO_040_076 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_040_076))
\r
2184 #define ADDR_GPIO_INPUT_GPIO_100_136 0x40081308
\r
2185 #define MMCR_GPIO_INPUT_GPIO_100_136 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_100_136))
\r
2187 #define ADDR_GPIO_INPUT_GPIO_140_176 0x4008130C
\r
2188 #define MMCR_GPIO_INPUT_GPIO_140_176 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_140_176))
\r
2190 #define ADDR_GPIO_INPUT_GPIO_200_236 0x40081310
\r
2191 #define MMCR_GPIO_INPUT_GPIO_200_236 (*(VUINT32 *)(ADDR_GPIO_INPUT_GPIO_200_236))
\r
2193 #define ADDR_GPIO_LOCK_4 0x400813EC
\r
2194 #define MMCR_GPIO_LOCK_4 (*(VUINT32 *)(ADDR_GPIO_LOCK_4))
\r
2196 #define ADDR_GPIO_LOCK_3 0x400813F0
\r
2197 #define MMCR_GPIO_LOCK_3 (*(VUINT32 *)(ADDR_GPIO_LOCK_3))
\r
2199 #define ADDR_GPIO_LOCK_2 0x400813F4
\r
2200 #define MMCR_GPIO_LOCK_2 (*(VUINT32 *)(ADDR_GPIO_LOCK_2))
\r
2202 #define ADDR_GPIO_LOCK_1 0x400813F8
\r
2203 #define MMCR_GPIO_LOCK_1 (*(VUINT32 *)(ADDR_GPIO_LOCK_1))
\r
2205 #define ADDR_GPIO_LOCK_0 0x400813FC
\r
2206 #define MMCR_GPIO_LOCK_0 (*(VUINT32 *)(ADDR_GPIO_LOCK_0))
\r
2208 #define ADDR_GPIO000_PIN_CONTROL_2 0x40081500
\r
2209 #define MMCR_GPIO000_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO000_PIN_CONTROL_2))
\r
2211 #define ADDR_GPIO001_PIN_CONTROL_2 0x40081504
\r
2212 #define MMCR_GPIO001_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO001_PIN_CONTROL_2))
\r
2214 #define ADDR_GPIO002_PIN_CONTROL_2 0x40081508
\r
2215 #define MMCR_GPIO002_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO002_PIN_CONTROL_2))
\r
2217 #define ADDR_GPIO003_PIN_CONTROL_2 0x4008150C
\r
2218 #define MMCR_GPIO003_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO003_PIN_CONTROL_2))
\r
2220 #define ADDR_GPIO004_PIN_CONTROL_2 0x40081510
\r
2221 #define MMCR_GPIO004_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO004_PIN_CONTROL_2))
\r
2223 #define ADDR_GPIO005_PIN_CONTROL_2 0x40081514
\r
2224 #define MMCR_GPIO005_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO005_PIN_CONTROL_2))
\r
2226 #define ADDR_GPIO006_PIN_CONTROL_2 0x40081518
\r
2227 #define MMCR_GPIO006_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO006_PIN_CONTROL_2))
\r
2229 #define ADDR_GPIO007_PIN_CONTROL_2 0x4008151C
\r
2230 #define MMCR_GPIO007_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO007_PIN_CONTROL_2))
\r
2232 #define ADDR_GPIO010_PIN_CONTROL_2 0x40081520
\r
2233 #define MMCR_GPIO010_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO010_PIN_CONTROL_2))
\r
2235 #define ADDR_GPIO011_PIN_CONTROL_2 0x40081524
\r
2236 #define MMCR_GPIO011_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO011_PIN_CONTROL_2))
\r
2238 #define ADDR_GPIO012_PIN_CONTROL_2 0x40081528
\r
2239 #define MMCR_GPIO012_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO012_PIN_CONTROL_2))
\r
2241 #define ADDR_GPIO013_PIN_CONTROL_2 0x4008152C
\r
2242 #define MMCR_GPIO013_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO013_PIN_CONTROL_2))
\r
2244 #define ADDR_GPIO014_PIN_CONTROL_2 0x40081530
\r
2245 #define MMCR_GPIO014_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO014_PIN_CONTROL_2))
\r
2247 #define ADDR_GPIO015_PIN_CONTROL_2 0x40081534
\r
2248 #define MMCR_GPIO015_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO015_PIN_CONTROL_2))
\r
2250 #define ADDR_GPIO016_PIN_CONTROL_2 0x40081538
\r
2251 #define MMCR_GPIO016_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO016_PIN_CONTROL_2))
\r
2253 #define ADDR_GPIO017_PIN_CONTROL_2 0x4008153C
\r
2254 #define MMCR_GPIO017_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO017_PIN_CONTROL_2))
\r
2256 #define ADDR_GPIO020_PIN_CONTROL_2 0x40081540
\r
2257 #define MMCR_GPIO020_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO020_PIN_CONTROL_2))
\r
2259 #define ADDR_GPIO021_PIN_CONTROL_2 0x40081544
\r
2260 #define MMCR_GPIO021_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO021_PIN_CONTROL_2))
\r
2262 #define ADDR_GPIO022_PIN_CONTROL_2 0x40081548
\r
2263 #define MMCR_GPIO022_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO022_PIN_CONTROL_2))
\r
2265 #define ADDR_GPIO023_PIN_CONTROL_2 0x4008154C
\r
2266 #define MMCR_GPIO023_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO023_PIN_CONTROL_2))
\r
2268 #define ADDR_GPIO024_PIN_CONTROL_2 0x40081550
\r
2269 #define MMCR_GPIO024_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO024_PIN_CONTROL_2))
\r
2271 #define ADDR_GPIO025_PIN_CONTROL_2 0x40081554
\r
2272 #define MMCR_GPIO025_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO025_PIN_CONTROL_2))
\r
2274 #define ADDR_GPIO026_PIN_CONTROL_2 0x40081558
\r
2275 #define MMCR_GPIO026_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO026_PIN_CONTROL_2))
\r
2277 #define ADDR_GPIO027_PIN_CONTROL_2 0x4008155C
\r
2278 #define MMCR_GPIO027_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO027_PIN_CONTROL_2))
\r
2280 #define ADDR_GPIO030_PIN_CONTROL_2 0x40081560
\r
2281 #define MMCR_GPIO030_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO030_PIN_CONTROL_2))
\r
2283 #define ADDR_GPIO031_PIN_CONTROL_2 0x40081564
\r
2284 #define MMCR_GPIO031_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO031_PIN_CONTROL_2))
\r
2286 #define ADDR_GPIO032_PIN_CONTROL_2 0x40081568
\r
2287 #define MMCR_GPIO032_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO032_PIN_CONTROL_2))
\r
2289 #define ADDR_GPIO033_PIN_CONTROL_2 0x4008156C
\r
2290 #define MMCR_GPIO033_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO033_PIN_CONTROL_2))
\r
2292 #define ADDR_GPIO034_PIN_CONTROL_2 0x40081570
\r
2293 #define MMCR_GPIO034_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO034_PIN_CONTROL_2))
\r
2295 #define ADDR_GPIO035_PIN_CONTROL_2 0x40081574
\r
2296 #define MMCR_GPIO035_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO035_PIN_CONTROL_2))
\r
2298 #define ADDR_GPIO036_PIN_CONTROL_2 0x40081578
\r
2299 #define MMCR_GPIO036_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO036_PIN_CONTROL_2))
\r
2301 #define ADDR_GPIO040_PIN_CONTROL_2 0x40081580
\r
2302 #define MMCR_GPIO040_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO040_PIN_CONTROL_2))
\r
2304 #define ADDR_GPIO041_PIN_CONTROL_2 0x40081584
\r
2305 #define MMCR_GPIO041_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO041_PIN_CONTROL_2))
\r
2307 #define ADDR_GPIO042_PIN_CONTROL_2 0x40081588
\r
2308 #define MMCR_GPIO042_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO042_PIN_CONTROL_2))
\r
2310 #define ADDR_GPIO043_PIN_CONTROL_2 0x4008158C
\r
2311 #define MMCR_GPIO043_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO043_PIN_CONTROL_2))
\r
2313 #define ADDR_GPIO044_PIN_CONTROL_2 0x40081590
\r
2314 #define MMCR_GPIO044_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO044_PIN_CONTROL_2))
\r
2316 #define ADDR_GPIO045_PIN_CONTROL_2 0x40081594
\r
2317 #define MMCR_GPIO045_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO045_PIN_CONTROL_2))
\r
2319 #define ADDR_GPIO046_PIN_CONTROL_2 0x40081598
\r
2320 #define MMCR_GPIO046_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO046_PIN_CONTROL_2))
\r
2322 #define ADDR_GPIO047_PIN_CONTROL_2 0x4008159C
\r
2323 #define MMCR_GPIO047_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO047_PIN_CONTROL_2))
\r
2325 #define ADDR_GPIO050_PIN_CONTROL_2 0x400815A0
\r
2326 #define MMCR_GPIO050_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO050_PIN_CONTROL_2))
\r
2328 #define ADDR_GPIO051_PIN_CONTROL_2 0x400815A4
\r
2329 #define MMCR_GPIO051_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO051_PIN_CONTROL_2))
\r
2331 #define ADDR_GPIO052_PIN_CONTROL_2 0x400815A8
\r
2332 #define MMCR_GPIO052_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO052_PIN_CONTROL_2))
\r
2334 #define ADDR_GPIO053_PIN_CONTROL_2 0x400815AC
\r
2335 #define MMCR_GPIO053_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO053_PIN_CONTROL_2))
\r
2337 #define ADDR_GPIO054_PIN_CONTROL_2 0x400815B0
\r
2338 #define MMCR_GPIO054_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO054_PIN_CONTROL_2))
\r
2340 #define ADDR_GPIO055_PIN_CONTROL_2 0x400815B4
\r
2341 #define MMCR_GPIO055_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO055_PIN_CONTROL_2))
\r
2343 #define ADDR_GPIO056_PIN_CONTROL_2 0x400815B8
\r
2344 #define MMCR_GPIO056_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO056_PIN_CONTROL_2))
\r
2346 #define ADDR_GPIO057_PIN_CONTROL_2 0x400815BC
\r
2347 #define MMCR_GPIO057_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO057_PIN_CONTROL_2))
\r
2349 #define ADDR_GPIO060_PIN_CONTROL_2 0x400815C0
\r
2350 #define MMCR_GPIO060_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO060_PIN_CONTROL_2))
\r
2352 #define ADDR_GPIO061_PIN_CONTROL_2 0x400815C4
\r
2353 #define MMCR_GPIO061_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO061_PIN_CONTROL_2))
\r
2355 #define ADDR_GPIO062_PIN_CONTROL_2 0x400815C8
\r
2356 #define MMCR_GPIO062_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO062_PIN_CONTROL_2))
\r
2358 #define ADDR_GPIO063_PIN_CONTROL_2 0x400815CC
\r
2359 #define MMCR_GPIO063_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO063_PIN_CONTROL_2))
\r
2361 #define ADDR_GPIO064_PIN_CONTROL_2 0x400815D0
\r
2362 #define MMCR_GPIO064_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO064_PIN_CONTROL_2))
\r
2364 #define ADDR_GPIO065_PIN_CONTROL_2 0x400815D4
\r
2365 #define MMCR_GPIO065_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO065_PIN_CONTROL_2))
\r
2367 #define ADDR_GPIO066_PIN_CONTROL_2 0x400815D8
\r
2368 #define MMCR_GPIO066_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO066_PIN_CONTROL_2))
\r
2370 #define ADDR_GPIO067_PIN_CONTROL_2 0x400815DC
\r
2371 #define MMCR_GPIO067_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO067_PIN_CONTROL_2))
\r
2373 #define ADDR_GPIO100_PIN_CONTROL_2 0x400815E0
\r
2374 #define MMCR_GPIO100_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO100_PIN_CONTROL_2))
\r
2376 #define ADDR_GPIO101_PIN_CONTROL_2 0x400815E4
\r
2377 #define MMCR_GPIO101_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO101_PIN_CONTROL_2))
\r
2379 #define ADDR_GPIO102_PIN_CONTROL_2 0x400815E8
\r
2380 #define MMCR_GPIO102_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO102_PIN_CONTROL_2))
\r
2382 #define ADDR_GPIO103_PIN_CONTROL_2 0x400815EC
\r
2383 #define MMCR_GPIO103_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO103_PIN_CONTROL_2))
\r
2385 #define ADDR_GPIO104_PIN_CONTROL_2 0x400815F0
\r
2386 #define MMCR_GPIO104_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO104_PIN_CONTROL_2))
\r
2388 #define ADDR_GPIO105_PIN_CONTROL_2 0x400815F4
\r
2389 #define MMCR_GPIO105_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO105_PIN_CONTROL_2))
\r
2391 #define ADDR_GPIO106_PIN_CONTROL_2 0x400815F8
\r
2392 #define MMCR_GPIO106_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO106_PIN_CONTROL_2))
\r
2394 #define ADDR_GPIO107_PIN_CONTROL_2 0x400815FC
\r
2395 #define MMCR_GPIO107_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO107_PIN_CONTROL_2))
\r
2397 #define ADDR_GPIO110_PIN_CONTROL_2 0x40081600
\r
2398 #define MMCR_GPIO110_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO110_PIN_CONTROL_2))
\r
2400 #define ADDR_GPIO111_PIN_CONTROL_2 0x40081604
\r
2401 #define MMCR_GPIO111_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO111_PIN_CONTROL_2))
\r
2403 #define ADDR_GPIO112_PIN_CONTROL_2 0x40081608
\r
2404 #define MMCR_GPIO112_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO112_PIN_CONTROL_2))
\r
2406 #define ADDR_GPIO113_PIN_CONTROL_2 0x4008160C
\r
2407 #define MMCR_GPIO113_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO113_PIN_CONTROL_2))
\r
2409 #define ADDR_GPIO114_PIN_CONTROL_2 0x40081610
\r
2410 #define MMCR_GPIO114_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO114_PIN_CONTROL_2))
\r
2412 #define ADDR_GPIO115_PIN_CONTROL_2 0x40081614
\r
2413 #define MMCR_GPIO115_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO115_PIN_CONTROL_2))
\r
2415 #define ADDR_GPIO116_PIN_CONTROL_2 0x40081618
\r
2416 #define MMCR_GPIO116_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO116_PIN_CONTROL_2))
\r
2418 #define ADDR_GPIO117_PIN_CONTROL_2 0x4008161C
\r
2419 #define MMCR_GPIO117_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO117_PIN_CONTROL_2))
\r
2421 #define ADDR_GPIO120_PIN_CONTROL_2 0x40081620
\r
2422 #define MMCR_GPIO120_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO120_PIN_CONTROL_2))
\r
2424 #define ADDR_GPIO121_PIN_CONTROL_2 0x40081624
\r
2425 #define MMCR_GPIO121_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO121_PIN_CONTROL_2))
\r
2427 #define ADDR_GPIO122_PIN_CONTROL_2 0x40081628
\r
2428 #define MMCR_GPIO122_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO122_PIN_CONTROL_2))
\r
2430 #define ADDR_GPIO123_PIN_CONTROL_2 0x4008162C
\r
2431 #define MMCR_GPIO123_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO123_PIN_CONTROL_2))
\r
2433 #define ADDR_GPIO124_PIN_CONTROL_2 0x40081630
\r
2434 #define MMCR_GPIO124_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO124_PIN_CONTROL_2))
\r
2436 #define ADDR_GPIO125_PIN_CONTROL_2 0x40081634
\r
2437 #define MMCR_GPIO125_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO125_PIN_CONTROL_2))
\r
2439 #define ADDR_GPIO126_PIN_CONTROL_2 0x40081638
\r
2440 #define MMCR_GPIO126_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO126_PIN_CONTROL_2))
\r
2442 #define ADDR_GPIO127_PIN_CONTROL_2 0x4008163C
\r
2443 #define MMCR_GPIO127_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO127_PIN_CONTROL_2))
\r
2445 #define ADDR_GPIO130_PIN_CONTROL_2 0x40081640
\r
2446 #define MMCR_GPIO130_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO130_PIN_CONTROL_2))
\r
2448 #define ADDR_GPIO131_PIN_CONTROL_2 0x40081644
\r
2449 #define MMCR_GPIO131_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO131_PIN_CONTROL_2))
\r
2451 #define ADDR_GPIO132_PIN_CONTROL_2 0x40081648
\r
2452 #define MMCR_GPIO132_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO132_PIN_CONTROL_2))
\r
2454 #define ADDR_GPIO133_PIN_CONTROL_2 0x4008164C
\r
2455 #define MMCR_GPIO133_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO133_PIN_CONTROL_2))
\r
2457 #define ADDR_GPIO134_PIN_CONTROL_2 0x40081650
\r
2458 #define MMCR_GPIO134_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO134_PIN_CONTROL_2))
\r
2460 #define ADDR_GPIO135_PIN_CONTROL_2 0x40081654
\r
2461 #define MMCR_GPIO135_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO135_PIN_CONTROL_2))
\r
2463 #define ADDR_GPIO136_PIN_CONTROL_2 0x40081658
\r
2464 #define MMCR_GPIO136_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO136_PIN_CONTROL_2))
\r
2466 #define ADDR_GPIO140_PIN_CONTROL_2 0x40081660
\r
2467 #define MMCR_GPIO140_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO140_PIN_CONTROL_2))
\r
2469 #define ADDR_GPIO141_PIN_CONTROL_2 0x40081664
\r
2470 #define MMCR_GPIO141_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO141_PIN_CONTROL_2))
\r
2472 #define ADDR_GPIO142_PIN_CONTROL_2 0x40081668
\r
2473 #define MMCR_GPIO142_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO142_PIN_CONTROL_2))
\r
2475 #define ADDR_GPIO143_PIN_CONTROL_2 0x4008166C
\r
2476 #define MMCR_GPIO143_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO143_PIN_CONTROL_2))
\r
2478 #define ADDR_GPIO144_PIN_CONTROL_2 0x40081670
\r
2479 #define MMCR_GPIO144_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO144_PIN_CONTROL_2))
\r
2481 #define ADDR_GPIO145_PIN_CONTROL_2 0x40081674
\r
2482 #define MMCR_GPIO145_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO145_PIN_CONTROL_2))
\r
2484 #define ADDR_GPIO146_PIN_CONTROL_2 0x40081678
\r
2485 #define MMCR_GPIO146_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO146_PIN_CONTROL_2))
\r
2487 #define ADDR_GPIO147_PIN_CONTROL_2 0x4008167C
\r
2488 #define MMCR_GPIO147_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO147_PIN_CONTROL_2))
\r
2490 #define ADDR_GPIO150_PIN_CONTROL_2 0x40081680
\r
2491 #define MMCR_GPIO150_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO150_PIN_CONTROL_2))
\r
2493 #define ADDR_GPIO151_PIN_CONTROL_2 0x40081684
\r
2494 #define MMCR_GPIO151_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO151_PIN_CONTROL_2))
\r
2496 #define ADDR_GPIO152_PIN_CONTROL_2 0x40081688
\r
2497 #define MMCR_GPIO152_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO152_PIN_CONTROL_2))
\r
2499 #define ADDR_GPIO153_PIN_CONTROL_2 0x4008168C
\r
2500 #define MMCR_GPIO153_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO153_PIN_CONTROL_2))
\r
2502 #define ADDR_GPIO154_PIN_CONTROL_2 0x40081690
\r
2503 #define MMCR_GPIO154_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO154_PIN_CONTROL_2))
\r
2505 #define ADDR_GPIO155_PIN_CONTROL_2 0x40081694
\r
2506 #define MMCR_GPIO155_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO155_PIN_CONTROL_2))
\r
2508 #define ADDR_GPIO156_PIN_CONTROL_2 0x40081698
\r
2509 #define MMCR_GPIO156_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO156_PIN_CONTROL_2))
\r
2511 #define ADDR_GPIO157_PIN_CONTROL_2 0x4008169C
\r
2512 #define MMCR_GPIO157_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO157_PIN_CONTROL_2))
\r
2514 #define ADDR_GPIO160_PIN_CONTROL_2 0x400816A0
\r
2515 #define MMCR_GPIO160_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO160_PIN_CONTROL_2))
\r
2517 #define ADDR_GPIO161_PIN_CONTROL_2 0x400816A4
\r
2518 #define MMCR_GPIO161_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO161_PIN_CONTROL_2))
\r
2520 #define ADDR_GPIO162_PIN_CONTROL_2 0x400816A8
\r
2521 #define MMCR_GPIO162_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO162_PIN_CONTROL_2))
\r
2523 #define ADDR_GPIO163_PIN_CONTROL_2 0x400816AC
\r
2524 #define MMCR_GPIO163_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO163_PIN_CONTROL_2))
\r
2526 #define ADDR_GPIO164_PIN_CONTROL_2 0x400816B0
\r
2527 #define MMCR_GPIO164_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO164_PIN_CONTROL_2))
\r
2529 #define ADDR_GPIO165_PIN_CONTROL_2 0x400816B4
\r
2530 #define MMCR_GPIO165_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO165_PIN_CONTROL_2))
\r
2532 #define ADDR_GPIO200_PIN_CONTROL_2 0x40081720
\r
2533 #define MMCR_GPIO200_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO200_PIN_CONTROL_2))
\r
2535 #define ADDR_GPIO201_PIN_CONTROL_2 0x40081724
\r
2536 #define MMCR_GPIO201_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO201_PIN_CONTROL_2))
\r
2538 #define ADDR_GPIO202_PIN_CONTROL_2 0x40081728
\r
2539 #define MMCR_GPIO202_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO202_PIN_CONTROL_2))
\r
2541 #define ADDR_GPIO203_PIN_CONTROL_2 0x4008172C
\r
2542 #define MMCR_GPIO203_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO203_PIN_CONTROL_2))
\r
2544 #define ADDR_GPIO204_PIN_CONTROL_2 0x40081730
\r
2545 #define MMCR_GPIO204_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO204_PIN_CONTROL_2))
\r
2547 #define ADDR_GPIO206_PIN_CONTROL_2 0x40081738
\r
2548 #define MMCR_GPIO206_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO206_PIN_CONTROL_2))
\r
2550 #define ADDR_GPIO210_PIN_CONTROL_2 0x40081740
\r
2551 #define MMCR_GPIO210_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO210_PIN_CONTROL_2))
\r
2553 #define ADDR_GPIO211_PIN_CONTROL_2 0x40081744
\r
2554 #define MMCR_GPIO211_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO211_PIN_CONTROL_2))
\r
2556 #define ADDR_GPIO212_PIN_CONTROL_2 0x40081748
\r
2557 #define MMCR_GPIO212_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO212_PIN_CONTROL_2))
\r
2559 #define ADDR_GPIO213_PIN_CONTROL_2 0x4008174C
\r
2560 #define MMCR_GPIO213_PIN_CONTROL_2 (*(VUINT32 *)(ADDR_GPIO213_PIN_CONTROL_2))
\r
2562 /***************************************************************
\r
2564 ***************************************************************/
\r
2565 #define ADDR_DMA_MAIN_CONTROL 0x40002400
\r
2566 #define MMCR_DMA_MAIN_CONTROL (*(VUINT8 *)(ADDR_DMA_MAIN_CONTROL))
\r
2568 #define ADDR_DMA_AFIFO_DATA 0x40002404
\r
2569 #define MMCR_DMA_AFIFO_DATA (*(VUINT32 *)(ADDR_DMA_AFIFO_DATA))
\r
2571 #define ADDR_DMA_MAIN_DEBUG 0x40002408
\r
2572 #define MMCR_DMA_MAIN_DEBUG (*(VUINT8 *)(ADDR_DMA_MAIN_DEBUG))
\r
2574 #define ADDR_DMA_CH0_ACTIVATE 0x40002410
\r
2575 #define MMCR_DMA_CH0_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH0_ACTIVATE))
\r
2577 #define ADDR_DMA_CH0_MEMORY_START_ADDRESS 0x40002414
\r
2578 #define MMCR_DMA_CH0_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_START_ADDRESS))
\r
2580 #define ADDR_DMA_CH0_MEMORY_END_ADDRESS 0x40002418
\r
2581 #define MMCR_DMA_CH0_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_MEMORY_END_ADDRESS))
\r
2583 #define ADDR_DMA_CH0_AHB_ADDRESS 0x4000241C
\r
2584 #define MMCR_DMA_CH0_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH0_AHB_ADDRESS))
\r
2586 #define ADDR_DMA_CH0_CONTROL 0x40002420
\r
2587 #define MMCR_DMA_CH0_CONTROL (*(VUINT32 *)(ADDR_DMA_CH0_CONTROL))
\r
2589 #define ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS 0x40002424
\r
2590 #define MMCR_DMA_CH0_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_STATUS))
\r
2592 #define ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE 0x40002428
\r
2593 #define MMCR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH0_CHANNEL_INTERRUPT_ENABLE))
\r
2595 #define ADDR_DMA_CH0_TEST 0x4000242C
\r
2596 #define MMCR_DMA_CH0_TEST (*(VUINT32 *)(ADDR_DMA_CH0_TEST))
\r
2598 #define ADDR_DMA_CH1_ACTIVATE 0x40002430
\r
2599 #define MMCR_DMA_CH1_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH1_ACTIVATE))
\r
2601 #define ADDR_DMA_CH1_MEMORY_START_ADDRESS 0x40002434
\r
2602 #define MMCR_DMA_CH1_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_START_ADDRESS))
\r
2604 #define ADDR_DMA_CH1_MEMORY_END_ADDRESS 0x40002438
\r
2605 #define MMCR_DMA_CH1_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_MEMORY_END_ADDRESS))
\r
2607 #define ADDR_DMA_CH1_AHB_ADDRESS 0x4000243C
\r
2608 #define MMCR_DMA_CH1_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH1_AHB_ADDRESS))
\r
2610 #define ADDR_DMA_CH1_CONTROL 0x40002440
\r
2611 #define MMCR_DMA_CH1_CONTROL (*(VUINT32 *)(ADDR_DMA_CH1_CONTROL))
\r
2613 #define ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS 0x40002444
\r
2614 #define MMCR_DMA_CH1_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_STATUS))
\r
2616 #define ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE 0x40002448
\r
2617 #define MMCR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH1_CHANNEL_INTERRUPT_ENABLE))
\r
2619 #define ADDR_DMA_CH1_TEST 0x4000244C
\r
2620 #define MMCR_DMA_CH1_TEST (*(VUINT32 *)(ADDR_DMA_CH1_TEST))
\r
2622 #define ADDR_DMA_CH10_ACTIVATE 0x40002550
\r
2623 #define MMCR_DMA_CH10_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH10_ACTIVATE))
\r
2625 #define ADDR_DMA_CH10_MEMORY_START_ADDRESS 0x40002554
\r
2626 #define MMCR_DMA_CH10_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_START_ADDRESS))
\r
2628 #define ADDR_DMA_CH10_MEMORY_END_ADDRESS 0x40002558
\r
2629 #define MMCR_DMA_CH10_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_MEMORY_END_ADDRESS))
\r
2631 #define ADDR_DMA_CH10_AHB_ADDRESS 0x4000255C
\r
2632 #define MMCR_DMA_CH10_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH10_AHB_ADDRESS))
\r
2634 #define ADDR_DMA_CH10_CONTROL 0x40002560
\r
2635 #define MMCR_DMA_CH10_CONTROL (*(VUINT32 *)(ADDR_DMA_CH10_CONTROL))
\r
2637 #define ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS 0x40002564
\r
2638 #define MMCR_DMA_CH10_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_STATUS))
\r
2640 #define ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE 0x40002568
\r
2641 #define MMCR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH10_CHANNEL_INTERRUPT_ENABLE))
\r
2643 #define ADDR_DMA_CH10_TEST 0x4000256C
\r
2644 #define MMCR_DMA_CH10_TEST (*(VUINT32 *)(ADDR_DMA_CH10_TEST))
\r
2646 #define ADDR_DMA_CH11_ACTIVATE 0x40002570
\r
2647 #define MMCR_DMA_CH11_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH11_ACTIVATE))
\r
2649 #define ADDR_DMA_CH11_MEMORY_START_ADDRESS 0x40002574
\r
2650 #define MMCR_DMA_CH11_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_START_ADDRESS))
\r
2652 #define ADDR_DMA_CH11_MEMORY_END_ADDRESS 0x40002578
\r
2653 #define MMCR_DMA_CH11_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_MEMORY_END_ADDRESS))
\r
2655 #define ADDR_DMA_CH11_AHB_ADDRESS 0x4000257C
\r
2656 #define MMCR_DMA_CH11_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH11_AHB_ADDRESS))
\r
2658 #define ADDR_DMA_CH11_CONTROL 0x40002580
\r
2659 #define MMCR_DMA_CH11_CONTROL (*(VUINT32 *)(ADDR_DMA_CH11_CONTROL))
\r
2661 #define ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS 0x40002584
\r
2662 #define MMCR_DMA_CH11_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_STATUS))
\r
2664 #define ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE 0x40002588
\r
2665 #define MMCR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH11_CHANNEL_INTERRUPT_ENABLE))
\r
2667 #define ADDR_DMA_CH11_TEST 0x4000258C
\r
2668 #define MMCR_DMA_CH11_TEST (*(VUINT32 *)(ADDR_DMA_CH11_TEST))
\r
2670 #define ADDR_DMA_CH2_ACTIVATE 0x40002450
\r
2671 #define MMCR_DMA_CH2_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH2_ACTIVATE))
\r
2673 #define ADDR_DMA_CH2_MEMORY_START_ADDRESS 0x40002454
\r
2674 #define MMCR_DMA_CH2_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_START_ADDRESS))
\r
2676 #define ADDR_DMA_CH2_MEMORY_END_ADDRESS 0x40002458
\r
2677 #define MMCR_DMA_CH2_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_MEMORY_END_ADDRESS))
\r
2679 #define ADDR_DMA_CH2_AHB_ADDRESS 0x4000245C
\r
2680 #define MMCR_DMA_CH2_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH2_AHB_ADDRESS))
\r
2682 #define ADDR_DMA_CH2_CONTROL 0x40002460
\r
2683 #define MMCR_DMA_CH2_CONTROL (*(VUINT32 *)(ADDR_DMA_CH2_CONTROL))
\r
2685 #define ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS 0x40002464
\r
2686 #define MMCR_DMA_CH2_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_STATUS))
\r
2688 #define ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE 0x40002468
\r
2689 #define MMCR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH2_CHANNEL_INTERRUPT_ENABLE))
\r
2691 #define ADDR_DMA_CH2_TEST 0x4000246C
\r
2692 #define MMCR_DMA_CH2_TEST (*(VUINT32 *)(ADDR_DMA_CH2_TEST))
\r
2694 #define ADDR_DMA_CH3_ACTIVATE 0x40002470
\r
2695 #define MMCR_DMA_CH3_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH3_ACTIVATE))
\r
2697 #define ADDR_DMA_CH3_MEMORY_START_ADDRESS 0x40002474
\r
2698 #define MMCR_DMA_CH3_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_START_ADDRESS))
\r
2700 #define ADDR_DMA_CH3_MEMORY_END_ADDRESS 0x40002478
\r
2701 #define MMCR_DMA_CH3_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_MEMORY_END_ADDRESS))
\r
2703 #define ADDR_DMA_CH3_AHB_ADDRESS 0x4000247C
\r
2704 #define MMCR_DMA_CH3_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH3_AHB_ADDRESS))
\r
2706 #define ADDR_DMA_CH3_CONTROL 0x40002480
\r
2707 #define MMCR_DMA_CH3_CONTROL (*(VUINT32 *)(ADDR_DMA_CH3_CONTROL))
\r
2709 #define ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS 0x40002484
\r
2710 #define MMCR_DMA_CH3_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_STATUS))
\r
2712 #define ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE 0x40002488
\r
2713 #define MMCR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH3_CHANNEL_INTERRUPT_ENABLE))
\r
2715 #define ADDR_DMA_CH3_TEST 0x4000248C
\r
2716 #define MMCR_DMA_CH3_TEST (*(VUINT32 *)(ADDR_DMA_CH3_TEST))
\r
2718 #define ADDR_DMA_CH4_ACTIVATE 0x40002490
\r
2719 #define MMCR_DMA_CH4_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH4_ACTIVATE))
\r
2721 #define ADDR_DMA_CH4_MEMORY_START_ADDRESS 0x40002494
\r
2722 #define MMCR_DMA_CH4_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_START_ADDRESS))
\r
2724 #define ADDR_DMA_CH4_MEMORY_END_ADDRESS 0x40002498
\r
2725 #define MMCR_DMA_CH4_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_MEMORY_END_ADDRESS))
\r
2727 #define ADDR_DMA_CH4_AHB_ADDRESS 0x4000249C
\r
2728 #define MMCR_DMA_CH4_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH4_AHB_ADDRESS))
\r
2730 #define ADDR_DMA_CH4_CONTROL 0x400024A0
\r
2731 #define MMCR_DMA_CH4_CONTROL (*(VUINT32 *)(ADDR_DMA_CH4_CONTROL))
\r
2733 #define ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS 0x400024A4
\r
2734 #define MMCR_DMA_CH4_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_STATUS))
\r
2736 #define ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE 0x400024A8
\r
2737 #define MMCR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH4_CHANNEL_INTERRUPT_ENABLE))
\r
2739 #define ADDR_DMA_CH4_TEST 0x400024AC
\r
2740 #define MMCR_DMA_CH4_TEST (*(VUINT32 *)(ADDR_DMA_CH4_TEST))
\r
2742 #define ADDR_DMA_CH5_ACTIVATE 0x400024B0
\r
2743 #define MMCR_DMA_CH5_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH5_ACTIVATE))
\r
2745 #define ADDR_DMA_CH5_MEMORY_START_ADDRESS 0x400024B4
\r
2746 #define MMCR_DMA_CH5_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_START_ADDRESS))
\r
2748 #define ADDR_DMA_CH5_MEMORY_END_ADDRESS 0x400024B8
\r
2749 #define MMCR_DMA_CH5_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_MEMORY_END_ADDRESS))
\r
2751 #define ADDR_DMA_CH5_AHB_ADDRESS 0x400024BC
\r
2752 #define MMCR_DMA_CH5_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH5_AHB_ADDRESS))
\r
2754 #define ADDR_DMA_CH5_CONTROL 0x400024C0
\r
2755 #define MMCR_DMA_CH5_CONTROL (*(VUINT32 *)(ADDR_DMA_CH5_CONTROL))
\r
2757 #define ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS 0x400024C4
\r
2758 #define MMCR_DMA_CH5_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_STATUS))
\r
2760 #define ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE 0x400024C8
\r
2761 #define MMCR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH5_CHANNEL_INTERRUPT_ENABLE))
\r
2763 #define ADDR_DMA_CH5_TEST 0x400024CC
\r
2764 #define MMCR_DMA_CH5_TEST (*(VUINT32 *)(ADDR_DMA_CH5_TEST))
\r
2766 #define ADDR_DMA_CH6_ACTIVATE 0x400024D0
\r
2767 #define MMCR_DMA_CH6_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH6_ACTIVATE))
\r
2769 #define ADDR_DMA_CH6_MEMORY_START_ADDRESS 0x400024D4
\r
2770 #define MMCR_DMA_CH6_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_START_ADDRESS))
\r
2772 #define ADDR_DMA_CH6_MEMORY_END_ADDRESS 0x400024D8
\r
2773 #define MMCR_DMA_CH6_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_MEMORY_END_ADDRESS))
\r
2775 #define ADDR_DMA_CH6_AHB_ADDRESS 0x400024DC
\r
2776 #define MMCR_DMA_CH6_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH6_AHB_ADDRESS))
\r
2778 #define ADDR_DMA_CH6_CONTROL 0x4.00E+05
\r
2779 #define MMCR_DMA_CH6_CONTROL (*(VUINT32 *)(ADDR_DMA_CH6_CONTROL))
\r
2781 #define ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS 0x4.00E+09
\r
2782 #define MMCR_DMA_CH6_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_STATUS))
\r
2784 #define ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE 0x4.00E+13
\r
2785 #define MMCR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH6_CHANNEL_INTERRUPT_ENABLE))
\r
2787 #define ADDR_DMA_CH6_TEST 0x400024EC
\r
2788 #define MMCR_DMA_CH6_TEST (*(VUINT32 *)(ADDR_DMA_CH6_TEST))
\r
2790 #define ADDR_DMA_CH7_ACTIVATE 0x400024F0
\r
2791 #define MMCR_DMA_CH7_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH7_ACTIVATE))
\r
2793 #define ADDR_DMA_CH7_MEMORY_START_ADDRESS 0x400024F4
\r
2794 #define MMCR_DMA_CH7_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_START_ADDRESS))
\r
2796 #define ADDR_DMA_CH7_MEMORY_END_ADDRESS 0x400024F8
\r
2797 #define MMCR_DMA_CH7_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_MEMORY_END_ADDRESS))
\r
2799 #define ADDR_DMA_CH7_AHB_ADDRESS 0x400024FC
\r
2800 #define MMCR_DMA_CH7_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH7_AHB_ADDRESS))
\r
2802 #define ADDR_DMA_CH7_CONTROL 0x40002500
\r
2803 #define MMCR_DMA_CH7_CONTROL (*(VUINT32 *)(ADDR_DMA_CH7_CONTROL))
\r
2805 #define ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS 0x40002504
\r
2806 #define MMCR_DMA_CH7_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_STATUS))
\r
2808 #define ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE 0x40002508
\r
2809 #define MMCR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH7_CHANNEL_INTERRUPT_ENABLE))
\r
2811 #define ADDR_DMA_CH7_TEST 0x4000250C
\r
2812 #define MMCR_DMA_CH7_TEST (*(VUINT32 *)(ADDR_DMA_CH7_TEST))
\r
2814 #define ADDR_DMA_CH8_ACTIVATE 0x40002510
\r
2815 #define MMCR_DMA_CH8_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH8_ACTIVATE))
\r
2817 #define ADDR_DMA_CH8_MEMORY_START_ADDRESS 0x40002514
\r
2818 #define MMCR_DMA_CH8_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_START_ADDRESS))
\r
2820 #define ADDR_DMA_CH8_MEMORY_END_ADDRESS 0x40002518
\r
2821 #define MMCR_DMA_CH8_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_MEMORY_END_ADDRESS))
\r
2823 #define ADDR_DMA_CH8_AHB_ADDRESS 0x4000251C
\r
2824 #define MMCR_DMA_CH8_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH8_AHB_ADDRESS))
\r
2826 #define ADDR_DMA_CH8_CONTROL 0x40002520
\r
2827 #define MMCR_DMA_CH8_CONTROL (*(VUINT32 *)(ADDR_DMA_CH8_CONTROL))
\r
2829 #define ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS 0x40002524
\r
2830 #define MMCR_DMA_CH8_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_STATUS))
\r
2832 #define ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE 0x40002528
\r
2833 #define MMCR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH8_CHANNEL_INTERRUPT_ENABLE))
\r
2835 #define ADDR_DMA_CH8_TEST 0x4000252C
\r
2836 #define MMCR_DMA_CH8_TEST (*(VUINT32 *)(ADDR_DMA_CH8_TEST))
\r
2838 #define ADDR_DMA_CH9_ACTIVATE 0x40002530
\r
2839 #define MMCR_DMA_CH9_ACTIVATE (*(VUINT32 *)(ADDR_DMA_CH9_ACTIVATE))
\r
2841 #define ADDR_DMA_CH9_MEMORY_START_ADDRESS 0x40002534
\r
2842 #define MMCR_DMA_CH9_MEMORY_START_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_START_ADDRESS))
\r
2844 #define ADDR_DMA_CH9_MEMORY_END_ADDRESS 0x40002538
\r
2845 #define MMCR_DMA_CH9_MEMORY_END_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_MEMORY_END_ADDRESS))
\r
2847 #define ADDR_DMA_CH9_AHB_ADDRESS 0x4000253C
\r
2848 #define MMCR_DMA_CH9_AHB_ADDRESS (*(VUINT32 *)(ADDR_DMA_CH9_AHB_ADDRESS))
\r
2850 #define ADDR_DMA_CH9_CONTROL 0x40002540
\r
2851 #define MMCR_DMA_CH9_CONTROL (*(VUINT32 *)(ADDR_DMA_CH9_CONTROL))
\r
2853 #define ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS 0x40002544
\r
2854 #define MMCR_DMA_CH9_CHANNEL_INTERRUPT_STATUS (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_STATUS))
\r
2856 #define ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE 0x40002548
\r
2857 #define MMCR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE (*(VUINT32 *)(ADDR_DMA_CH9_CHANNEL_INTERRUPT_ENABLE))
\r
2859 #define ADDR_DMA_CH9_TEST 0x4000254C
\r
2860 #define MMCR_DMA_CH9_TEST (*(VUINT32 *)(ADDR_DMA_CH9_TEST))
\r
2862 #endif /*SMSCMMCR_H_*/
\r
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