begriffs open source - freertos/blob - portable/GCC/ARM_CM55/non_secure/portasm.c

   1 /*
   2  * FreeRTOS Kernel V11.0.1
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28
  29 /* Standard includes. */
  30 #include <stdint.h>
  31
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  33  * is defined correctly and privileged functions are placed in correct sections. */
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  35
  36 /* Portasm includes. */
  37 #include "portasm.h"
  38
  39 /* System call numbers includes. */
  40 #include "mpu_syscall_numbers.h"
  41
  42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  43  * header files. */
  44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  45
  46 #if ( configENABLE_MPU == 1 )
  47
  48     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  49     {
  50         __asm volatile
  51         (
  52             " .syntax unified                                 \n"
  53             "                                                 \n"
  54             " program_mpu_first_task:                         \n"
  55             "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  56             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
  57             "                                                 \n"
  58             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
  59             "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  60             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  61             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
  62             "    str r2, [r1]                                 \n" /* Disable MPU. */
  63             "                                                 \n"
  64             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
  65             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
  66             "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
  67             "    str r1, [r2]                                 \n" /* Program MAIR0. */
  68             "                                                 \n"
  69             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
  70             "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
  71             "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  72             "                                                 \n"
  73             "    movs r3, #4                                  \n" /* r3 = 4. */
  74             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
  75             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  76             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  77             "                                                 \n"
  78             #if ( configTOTAL_MPU_REGIONS == 16 )
  79                 "    movs r3, #8                                  \n" /* r3 = 8. */
  80                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
  81                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  82                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  83                 "    movs r3, #12                                 \n" /* r3 = 12. */
  84                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
  85                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  86                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  87             #endif /* configTOTAL_MPU_REGIONS == 16 */
  88             "                                                 \n"
  89             "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  90             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  91             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
  92             "    str r2, [r1]                                 \n" /* Enable MPU. */
  93             "    dsb                                          \n" /* Force memory writes before continuing. */
  94             "                                                 \n"
  95             " restore_context_first_task:                     \n"
  96             "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  97             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
  98             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
  99             "                                                 \n"
 100             " restore_special_regs_first_task:                \n"
 101             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 102             "    msr psp, r3                                  \n"
 103             "    msr psplim, r4                               \n"
 104             "    msr control, r5                              \n"
 105             "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 106             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 107             "                                                 \n"
 108             " restore_general_regs_first_task:                \n"
 109             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 110             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 111             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 112             "                                                 \n"
 113             " restore_context_done_first_task:                \n"
 114             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 115             "    mov r0, #0                                   \n"
 116             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
 117             "    bx lr                                        \n"
 118             "                                                 \n"
 119             " .align 4                                        \n"
 120             " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
 121             " xSecureContextConst2: .word xSecureContext      \n"
 122             " xMPUCTRLConst2: .word 0xe000ed94                \n"
 123             " xMAIR0Const2: .word 0xe000edc0                  \n"
 124             " xRNRConst2: .word 0xe000ed98                    \n"
 125             " xRBARConst2: .word 0xe000ed9c                   \n"
 126         );
 127     }
 128
 129 #else /* configENABLE_MPU */
 130
 131     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 132     {
 133         __asm volatile
 134         (
 135             "   .syntax unified                                 \n"
 136             "                                                   \n"
 137             "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 138             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
 139             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 140             "                                                   \n"
 141             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
 142             "   ldr  r4, xSecureContextConst2                   \n"
 143             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
 144             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
 145             "   movs r1, #2                                     \n" /* r1 = 2. */
 146             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
 147             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
 148             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
 149             "   isb                                             \n"
 150             "   mov  r0, #0                                     \n"
 151             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
 152             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
 153             "   .align 4                                        \n"
 154             "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
 155             "xSecureContextConst2: .word xSecureContext         \n"
 156         );
 157     }
 158
 159 #endif /* configENABLE_MPU */
 160 /*-----------------------------------------------------------*/
 161
 162 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 163 {
 164     __asm volatile
 165     (
 166         "   .syntax unified                                 \n"
 167         "                                                   \n"
 168         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 169         "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
 170         "   ite ne                                          \n"
 171         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 172         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 173         "   bx lr                                           \n" /* Return. */
 174         "                                                   \n"
 175         "   .align 4                                        \n"
 176         ::: "r0", "memory"
 177     );
 178 }
 179 /*-----------------------------------------------------------*/
 180
 181 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 182 {
 183     __asm volatile
 184     (
 185         "   .syntax unified                                 \n"
 186         "                                                   \n"
 187         "   mrs r0, control                                 \n" /* Read the CONTROL register. */
 188         "   bic r0, #1                                      \n" /* Clear the bit 0. */
 189         "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
 190         "   bx lr                                           \n" /* Return to the caller. */
 191         ::: "r0", "memory"
 192     );
 193 }
 194 /*-----------------------------------------------------------*/
 195
 196 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 197 {
 198     __asm volatile
 199     (
 200         "   .syntax unified                                 \n"
 201         "                                                   \n"
 202         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 203         "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
 204         "   msr control, r0                                 \n" /* CONTROL = r0. */
 205         "   bx lr                                           \n" /* Return to the caller. */
 206         ::: "r0", "memory"
 207     );
 208 }
 209 /*-----------------------------------------------------------*/
 210
 211 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 212 {
 213     __asm volatile
 214     (
 215         "   .syntax unified                                 \n"
 216         "                                                   \n"
 217         "   ldr r0, xVTORConst                              \n" /* Use the NVIC offset register to locate the stack. */
 218         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
 219         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
 220         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
 221         "   cpsie i                                         \n" /* Globally enable interrupts. */
 222         "   cpsie f                                         \n"
 223         "   dsb                                             \n"
 224         "   isb                                             \n"
 225         "   svc %0                                          \n" /* System call to start the first task. */
 226         "   nop                                             \n"
 227         "                                                   \n"
 228         "   .align 4                                        \n"
 229         "xVTORConst: .word 0xe000ed08                       \n"
 230         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 231     );
 232 }
 233 /*-----------------------------------------------------------*/
 234
 235 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 236 {
 237     __asm volatile
 238     (
 239         "   .syntax unified                                 \n"
 240         "                                                   \n"
 241         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
 242         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 243         "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 244         "   dsb                                             \n"
 245         "   isb                                             \n"
 246         "   bx lr                                           \n" /* Return. */
 247         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 248     );
 249 }
 250 /*-----------------------------------------------------------*/
 251
 252 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 253 {
 254     __asm volatile
 255     (
 256         "   .syntax unified                                 \n"
 257         "                                                   \n"
 258         "   msr basepri, r0                                 \n" /* basepri = ulMask. */
 259         "   dsb                                             \n"
 260         "   isb                                             \n"
 261         "   bx lr                                           \n" /* Return. */
 262         ::: "memory"
 263     );
 264 }
 265 /*-----------------------------------------------------------*/
 266
 267 #if ( configENABLE_MPU == 1 )
 268
 269     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 270     {
 271         __asm volatile
 272         (
 273             " .syntax unified                                 \n"
 274             " .extern SecureContext_SaveContext               \n"
 275             " .extern SecureContext_LoadContext               \n"
 276             "                                                 \n"
 277             " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 278             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 279             " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 280             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 281             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
 282             "                                                 \n"
 283             " cbz r0, save_ns_context                         \n" /* No secure context to save. */
 284             " save_s_context:                                 \n"
 285             "    push {r0-r2, lr}                             \n"
 286             "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 287             "    pop {r0-r2, lr}                              \n"
 288             "                                                 \n"
 289             " save_ns_context:                                \n"
 290             "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
 291             "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 292             "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 293             "                                                 \n"
 294             " save_general_regs:                              \n"
 295             "    mrs r3, psp                                  \n"
 296             "                                                 \n"
 297             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 298                 "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
 299                 "    tst lr, #0x10                                \n"
 300                 "    ittt eq                                      \n"
 301                 "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
 302                 "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
 303                 "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
 304                 "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
 305             #endif /* configENABLE_FPU || configENABLE_MVE */
 306             "                                                 \n"
 307             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
 308             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
 309             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
 310             "                                                 \n"
 311             " save_special_regs:                              \n"
 312             "    mrs r3, psp                                  \n" /* r3 = PSP. */
 313             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
 314             "    mrs r5, control                              \n" /* r5 = CONTROL. */
 315             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
 316             "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
 317             "                                                 \n"
 318             " select_next_task:                               \n"
 319             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 320             "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 321             "    dsb                                          \n"
 322             "    isb                                          \n"
 323             "    bl vTaskSwitchContext                        \n"
 324             "    mov r0, #0                                   \n" /* r0 = 0. */
 325             "    msr basepri, r0                              \n" /* Enable interrupts. */
 326             "                                                 \n"
 327             " program_mpu:                                    \n"
 328             "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 329             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
 330             "                                                 \n"
 331             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
 332             "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 333             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 334             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
 335             "    str r2, [r1]                                 \n" /* Disable MPU. */
 336             "                                                 \n"
 337             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
 338             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
 339             "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
 340             "    str r1, [r2]                                 \n" /* Program MAIR0. */
 341             "                                                 \n"
 342             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
 343             "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
 344             "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 345             "                                                 \n"
 346             "    movs r3, #4                                  \n" /* r3 = 4. */
 347             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
 348             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 349             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 350             "                                                 \n"
 351             #if ( configTOTAL_MPU_REGIONS == 16 )
 352                 "    movs r3, #8                                  \n" /* r3 = 8. */
 353                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
 354                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 355                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 356                 "    movs r3, #12                                 \n" /* r3 = 12. */
 357                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
 358                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 359                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 360             #endif /* configTOTAL_MPU_REGIONS == 16 */
 361             "                                                 \n"
 362             "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 363             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
 364             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
 365             "   str r2, [r1]                                  \n" /* Enable MPU. */
 366             "   dsb                                           \n" /* Force memory writes before continuing. */
 367             "                                                 \n"
 368             " restore_context:                                \n"
 369             "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 370             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 371             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 372             "                                                 \n"
 373             " restore_special_regs:                           \n"
 374             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 375             "    msr psp, r3                                  \n"
 376             "    msr psplim, r4                               \n"
 377             "    msr control, r5                              \n"
 378             "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 379             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 380             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
 381             "                                                 \n"
 382             " restore_s_context:                              \n"
 383             "    push {r1-r3, lr}                             \n"
 384             "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 385             "    pop {r1-r3, lr}                              \n"
 386             "                                                 \n"
 387             " restore_ns_context:                             \n"
 388             "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
 389             "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 390             "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 391             "                                                 \n"
 392             " restore_general_regs:                           \n"
 393             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 394             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 395             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 396             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 397                 "    tst lr, #0x10                                \n"
 398                 "    ittt eq                                      \n"
 399                 "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
 400                 "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
 401                 "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
 402             #endif /* configENABLE_FPU || configENABLE_MVE */
 403             "                                                 \n"
 404             " restore_context_done:                           \n"
 405             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 406             "    bx lr                                        \n"
 407             "                                                 \n"
 408             " .align 4                                        \n"
 409             " pxCurrentTCBConst: .word pxCurrentTCB           \n"
 410             " xSecureContextConst: .word xSecureContext       \n"
 411             " xMPUCTRLConst: .word 0xe000ed94                 \n"
 412             " xMAIR0Const: .word 0xe000edc0                   \n"
 413             " xRNRConst: .word 0xe000ed98                     \n"
 414             " xRBARConst: .word 0xe000ed9c                    \n"
 415             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 416         );
 417     }
 418
 419 #else /* configENABLE_MPU */
 420
 421     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 422     {
 423         __asm volatile
 424         (
 425             "   .syntax unified                                 \n"
 426             "   .extern SecureContext_SaveContext               \n"
 427             "   .extern SecureContext_LoadContext               \n"
 428             "                                                   \n"
 429             "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 430             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 431             "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 432             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 433             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
 434             "                                                   \n"
 435             "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
 436             "   push {r0-r2, r14}                               \n"
 437             "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 438             "   pop {r0-r3}                                     \n" /* LR is now in r3. */
 439             "   mov lr, r3                                      \n" /* LR = r3. */
 440             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 441             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 442             "                                                   \n"
 443             "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 444             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
 445             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
 446             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 447             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 448             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 449             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 450             "   b select_next_task                              \n"
 451             "                                                   \n"
 452             " save_ns_context:                                  \n"
 453             "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 454             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 455             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 456                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 457                 "   it eq                                       \n"
 458                 "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
 459             #endif /* configENABLE_FPU || configENABLE_MVE */
 460             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
 461             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 462             "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
 463             "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
 464             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 465             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 466             "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
 467             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 468             "                                                   \n"
 469             " select_next_task:                                 \n"
 470             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 471             "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 472             "   dsb                                             \n"
 473             "   isb                                             \n"
 474             "   bl vTaskSwitchContext                           \n"
 475             "   mov r0, #0                                      \n" /* r0 = 0. */
 476             "   msr basepri, r0                                 \n" /* Enable interrupts. */
 477             "                                                   \n"
 478             "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 479             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 480             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 481             "                                                   \n"
 482             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
 483             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
 484             "   mov lr, r4                                      \n" /* LR = r4. */
 485             "   ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 486             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
 487             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
 488             "   ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 489             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 490             "   push {r2, r4}                                   \n"
 491             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 492             "   pop {r2, r4}                                    \n"
 493             "   mov lr, r4                                      \n" /* LR = r4. */
 494             "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 495             "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 496             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 497             "   bx lr                                           \n"
 498             "                                                   \n"
 499             " restore_ns_context:                               \n"
 500             "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
 501             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 502                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 503                 "   it eq                                       \n"
 504                 "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
 505             #endif /* configENABLE_FPU || configENABLE_MVE */
 506             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 507             "   bx lr                                           \n"
 508             "                                                   \n"
 509             "   .align 4                                        \n"
 510             "pxCurrentTCBConst: .word pxCurrentTCB              \n"
 511             "xSecureContextConst: .word xSecureContext          \n"
 512             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 513         );
 514     }
 515
 516 #endif /* configENABLE_MPU */
 517 /*-----------------------------------------------------------*/
 518
 519 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 520
 521     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 522     {
 523         __asm volatile
 524         (
 525             ".syntax unified                \n"
 526             ".extern vPortSVCHandler_C      \n"
 527             ".extern vSystemCallEnter       \n"
 528             ".extern vSystemCallExit        \n"
 529             "                               \n"
 530             "tst lr, #4                     \n"
 531             "ite eq                         \n"
 532             "mrseq r0, msp                  \n"
 533             "mrsne r0, psp                  \n"
 534             "                               \n"
 535             "ldr r1, [r0, #24]              \n"
 536             "ldrb r2, [r1, #-2]             \n"
 537             "cmp r2, %0                     \n"
 538             "blt syscall_enter              \n"
 539             "cmp r2, %1                     \n"
 540             "beq syscall_exit               \n"
 541             "b vPortSVCHandler_C            \n"
 542             "                               \n"
 543             "syscall_enter:                 \n"
 544             "    mov r1, lr                 \n"
 545             "    b vSystemCallEnter         \n"
 546             "                               \n"
 547             "syscall_exit:                  \n"
 548             "    mov r1, lr                 \n"
 549             "    b vSystemCallExit          \n"
 550             "                               \n"
 551             : /* No outputs. */
 552             : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
 553             : "r0", "r1", "r2", "memory"
 554         );
 555     }
 556
 557 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 558
 559     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 560     {
 561         __asm volatile
 562         (
 563             "   .syntax unified                                 \n"
 564             "                                                   \n"
 565             "   tst lr, #4                                      \n"
 566             "   ite eq                                          \n"
 567             "   mrseq r0, msp                                   \n"
 568             "   mrsne r0, psp                                   \n"
 569             "   ldr r1, svchandler_address_const                \n"
 570             "   bx r1                                           \n"
 571             "                                                   \n"
 572             "   .align 4                                        \n"
 573             "svchandler_address_const: .word vPortSVCHandler_C  \n"
 574         );
 575     }
 576
 577 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 578 /*-----------------------------------------------------------*/
 579
 580 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 581 {
 582     __asm volatile
 583     (
 584         "   .syntax unified                                 \n"
 585         "                                                   \n"
 586         "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
 587         "   bx lr                                           \n" /* Return. */
 588         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
 589     );
 590 }
 591 /*-----------------------------------------------------------*/
 592
 593 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 594 {
 595     __asm volatile
 596     (
 597         "   .syntax unified                                 \n"
 598         "                                                   \n"
 599         "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
 600         "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
 601         "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
 602         "   it ne                                           \n"
 603         "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
 604         "   bx lr                                           \n" /* Return. */
 605         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
 606     );
 607 }
 608 /*-----------------------------------------------------------*/