begriffs open source - freertos/blob - portable/GCC/ARM_CM55/non_secure/portasm.c

   1 /*
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28
  29 /* Standard includes. */
  30 #include <stdint.h>
  31
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  33  * is defined correctly and privileged functions are placed in correct sections. */
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  35
  36 /* Portasm includes. */
  37 #include "portasm.h"
  38
  39 /* System call numbers includes. */
  40 #include "mpu_syscall_numbers.h"
  41
  42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  43  * header files. */
  44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  45
  46 #if ( configENABLE_MPU == 1 )
  47
  48     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  49     {
  50         __asm volatile
  51         (
  52             " .syntax unified                                 \n"
  53             "                                                 \n"
  54             " program_mpu_first_task:                         \n"
  55             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  56             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
  57             "                                                 \n"
  58             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
  59             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  60             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  61             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
  62             "    str r2, [r1]                                 \n" /* Disable MPU. */
  63             "                                                 \n"
  64             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
  65             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
  66             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
  67             "    str r1, [r2]                                 \n" /* Program MAIR0. */
  68             "                                                 \n"
  69             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
  70             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
  71             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  72             "                                                 \n"
  73             "    movs r3, #4                                  \n" /* r3 = 4. */
  74             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
  75             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  76             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  77             "                                                 \n"
  78             #if ( configTOTAL_MPU_REGIONS == 16 )
  79                 "    movs r3, #8                                  \n" /* r3 = 8. */
  80                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
  81                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  82                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  83                 "    movs r3, #12                                 \n" /* r3 = 12. */
  84                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
  85                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  86                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  87             #endif /* configTOTAL_MPU_REGIONS == 16 */
  88             "                                                 \n"
  89             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  90             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  91             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
  92             "    str r2, [r1]                                 \n" /* Enable MPU. */
  93             "    dsb                                          \n" /* Force memory writes before continuing. */
  94             "                                                 \n"
  95             " restore_context_first_task:                     \n"
  96             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  97             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
  98             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
  99             "                                                 \n"
 100             " restore_special_regs_first_task:                \n"
 101             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 102             "    msr psp, r3                                  \n"
 103             "    msr psplim, r4                               \n"
 104             "    msr control, r5                              \n"
 105             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 106             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 107             "                                                 \n"
 108             " restore_general_regs_first_task:                \n"
 109             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 110             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 111             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 112             "                                                 \n"
 113             " restore_context_done_first_task:                \n"
 114             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 115             "    mov r0, #0                                   \n"
 116             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
 117             "    bx lr                                        \n"
 118         );
 119     }
 120
 121 #else /* configENABLE_MPU */
 122
 123     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 124     {
 125         __asm volatile
 126         (
 127             "   .syntax unified                                 \n"
 128             "                                                   \n"
 129             "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 130             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
 131             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 132             "                                                   \n"
 133             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
 134             "   ldr  r4, =xSecureContext                        \n"
 135             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
 136             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
 137             "   movs r1, #2                                     \n" /* r1 = 2. */
 138             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
 139             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
 140             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
 141             "   isb                                             \n"
 142             "   mov  r0, #0                                     \n"
 143             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
 144             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
 145         );
 146     }
 147
 148 #endif /* configENABLE_MPU */
 149 /*-----------------------------------------------------------*/
 150
 151 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 152 {
 153     __asm volatile
 154     (
 155         "   .syntax unified                                 \n"
 156         "                                                   \n"
 157         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 158         "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
 159         "   ite ne                                          \n"
 160         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 161         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 162         "   bx lr                                           \n" /* Return. */
 163         ::: "r0", "memory"
 164     );
 165 }
 166 /*-----------------------------------------------------------*/
 167
 168 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 169 {
 170     __asm volatile
 171     (
 172         "   .syntax unified                                 \n"
 173         "                                                   \n"
 174         "   mrs r0, control                                 \n" /* Read the CONTROL register. */
 175         "   bic r0, #1                                      \n" /* Clear the bit 0. */
 176         "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
 177         "   bx lr                                           \n" /* Return to the caller. */
 178         ::: "r0", "memory"
 179     );
 180 }
 181 /*-----------------------------------------------------------*/
 182
 183 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 184 {
 185     __asm volatile
 186     (
 187         "   .syntax unified                                 \n"
 188         "                                                   \n"
 189         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 190         "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
 191         "   msr control, r0                                 \n" /* CONTROL = r0. */
 192         "   bx lr                                           \n" /* Return to the caller. */
 193         ::: "r0", "memory"
 194     );
 195 }
 196 /*-----------------------------------------------------------*/
 197
 198 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 199 {
 200     __asm volatile
 201     (
 202         "   .syntax unified                                 \n"
 203         "                                                   \n"
 204         "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
 205         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
 206         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
 207         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
 208         "   cpsie i                                         \n" /* Globally enable interrupts. */
 209         "   cpsie f                                         \n"
 210         "   dsb                                             \n"
 211         "   isb                                             \n"
 212         "   svc %0                                          \n" /* System call to start the first task. */
 213         "   nop                                             \n"
 214         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 215     );
 216 }
 217 /*-----------------------------------------------------------*/
 218
 219 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 220 {
 221     __asm volatile
 222     (
 223         "   .syntax unified                                 \n"
 224         "                                                   \n"
 225         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
 226         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 227         "   msr basepri, r1                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 228         "   dsb                                             \n"
 229         "   isb                                             \n"
 230         "   bx lr                                           \n" /* Return. */
 231         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 232     );
 233 }
 234 /*-----------------------------------------------------------*/
 235
 236 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 237 {
 238     __asm volatile
 239     (
 240         "   .syntax unified                                 \n"
 241         "                                                   \n"
 242         "   msr basepri, r0                                 \n" /* basepri = ulMask. */
 243         "   dsb                                             \n"
 244         "   isb                                             \n"
 245         "   bx lr                                           \n" /* Return. */
 246         ::: "memory"
 247     );
 248 }
 249 /*-----------------------------------------------------------*/
 250
 251 #if ( configENABLE_MPU == 1 )
 252
 253     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 254     {
 255         __asm volatile
 256         (
 257             " .syntax unified                                 \n"
 258             " .extern SecureContext_SaveContext               \n"
 259             " .extern SecureContext_LoadContext               \n"
 260             "                                                 \n"
 261             " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 262             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 263             " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 264             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 265             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
 266             "                                                 \n"
 267             " cbz r0, save_ns_context                         \n" /* No secure context to save. */
 268             " save_s_context:                                 \n"
 269             "    push {r0-r2, lr}                             \n"
 270             "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 271             "    pop {r0-r2, lr}                              \n"
 272             "                                                 \n"
 273             " save_ns_context:                                \n"
 274             "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
 275             "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 276             "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 277             "                                                 \n"
 278             " save_general_regs:                              \n"
 279             "    mrs r3, psp                                  \n"
 280             "                                                 \n"
 281             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 282                 "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
 283                 "    tst lr, #0x10                                \n"
 284                 "    ittt eq                                      \n"
 285                 "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
 286                 "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
 287                 "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
 288                 "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
 289             #endif /* configENABLE_FPU || configENABLE_MVE */
 290             "                                                 \n"
 291             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
 292             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
 293             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
 294             "                                                 \n"
 295             " save_special_regs:                              \n"
 296             "    mrs r3, psp                                  \n" /* r3 = PSP. */
 297             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
 298             "    mrs r5, control                              \n" /* r5 = CONTROL. */
 299             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
 300             "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
 301             "                                                 \n"
 302             " select_next_task:                               \n"
 303             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 304             "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 305             "    dsb                                          \n"
 306             "    isb                                          \n"
 307             "    bl vTaskSwitchContext                        \n"
 308             "    mov r0, #0                                   \n" /* r0 = 0. */
 309             "    msr basepri, r0                              \n" /* Enable interrupts. */
 310             "                                                 \n"
 311             " program_mpu:                                    \n"
 312             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 313             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
 314             "                                                 \n"
 315             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
 316             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 317             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 318             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
 319             "    str r2, [r1]                                 \n" /* Disable MPU. */
 320             "                                                 \n"
 321             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
 322             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
 323             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
 324             "    str r1, [r2]                                 \n" /* Program MAIR0. */
 325             "                                                 \n"
 326             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
 327             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
 328             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 329             "                                                 \n"
 330             "    movs r3, #4                                  \n" /* r3 = 4. */
 331             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
 332             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 333             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 334             "                                                 \n"
 335             #if ( configTOTAL_MPU_REGIONS == 16 )
 336                 "    movs r3, #8                                  \n" /* r3 = 8. */
 337                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
 338                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 339                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 340                 "    movs r3, #12                                 \n" /* r3 = 12. */
 341                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
 342                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 343                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 344             #endif /* configTOTAL_MPU_REGIONS == 16 */
 345             "                                                 \n"
 346             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 347             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
 348             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
 349             "   str r2, [r1]                                  \n" /* Enable MPU. */
 350             "   dsb                                           \n" /* Force memory writes before continuing. */
 351             "                                                 \n"
 352             " restore_context:                                \n"
 353             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 354             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 355             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 356             "                                                 \n"
 357             " restore_special_regs:                           \n"
 358             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 359             "    msr psp, r3                                  \n"
 360             "    msr psplim, r4                               \n"
 361             "    msr control, r5                              \n"
 362             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 363             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 364             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
 365             "                                                 \n"
 366             " restore_s_context:                              \n"
 367             "    push {r1-r3, lr}                             \n"
 368             "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 369             "    pop {r1-r3, lr}                              \n"
 370             "                                                 \n"
 371             " restore_ns_context:                             \n"
 372             "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
 373             "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 374             "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 375             "                                                 \n"
 376             " restore_general_regs:                           \n"
 377             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 378             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 379             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 380             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 381                 "    tst lr, #0x10                                \n"
 382                 "    ittt eq                                      \n"
 383                 "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
 384                 "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
 385                 "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
 386             #endif /* configENABLE_FPU || configENABLE_MVE */
 387             "                                                 \n"
 388             " restore_context_done:                           \n"
 389             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 390             "    bx lr                                        \n"
 391             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 392         );
 393     }
 394
 395 #else /* configENABLE_MPU */
 396
 397     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 398     {
 399         __asm volatile
 400         (
 401             "   .syntax unified                                 \n"
 402             "   .extern SecureContext_SaveContext               \n"
 403             "   .extern SecureContext_LoadContext               \n"
 404             "                                                   \n"
 405             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 406             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 407             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 408             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 409             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
 410             "                                                   \n"
 411             "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
 412             "   push {r0-r2, r14}                               \n"
 413             "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 414             "   pop {r0-r3}                                     \n" /* LR is now in r3. */
 415             "   mov lr, r3                                      \n" /* LR = r3. */
 416             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 417             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 418             "                                                   \n"
 419             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 420             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
 421             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
 422             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 423             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 424             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 425             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 426             "   b select_next_task                              \n"
 427             "                                                   \n"
 428             " save_ns_context:                                  \n"
 429             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 430             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 431             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 432                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 433                 "   it eq                                       \n"
 434                 "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
 435             #endif /* configENABLE_FPU || configENABLE_MVE */
 436             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
 437             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 438             "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
 439             "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
 440             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 441             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 442             "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
 443             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 444             "                                                   \n"
 445             " select_next_task:                                 \n"
 446             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 447             "   msr basepri, r0                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 448             "   dsb                                             \n"
 449             "   isb                                             \n"
 450             "   bl vTaskSwitchContext                           \n"
 451             "   mov r0, #0                                      \n" /* r0 = 0. */
 452             "   msr basepri, r0                                 \n" /* Enable interrupts. */
 453             "                                                   \n"
 454             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 455             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 456             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 457             "                                                   \n"
 458             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
 459             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
 460             "   mov lr, r4                                      \n" /* LR = r4. */
 461             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 462             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
 463             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
 464             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 465             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 466             "   push {r2, r4}                                   \n"
 467             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 468             "   pop {r2, r4}                                    \n"
 469             "   mov lr, r4                                      \n" /* LR = r4. */
 470             "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 471             "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 472             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 473             "   bx lr                                           \n"
 474             "                                                   \n"
 475             " restore_ns_context:                               \n"
 476             "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
 477             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 478                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 479                 "   it eq                                       \n"
 480                 "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
 481             #endif /* configENABLE_FPU || configENABLE_MVE */
 482             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 483             "   bx lr                                           \n"
 484             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 485         );
 486     }
 487
 488 #endif /* configENABLE_MPU */
 489 /*-----------------------------------------------------------*/
 490
 491 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 492
 493     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 494     {
 495         __asm volatile
 496         (
 497             ".syntax unified                \n"
 498             ".extern vPortSVCHandler_C      \n"
 499             ".extern vSystemCallEnter       \n"
 500             ".extern vSystemCallExit        \n"
 501             "                               \n"
 502             "tst lr, #4                     \n"
 503             "ite eq                         \n"
 504             "mrseq r0, msp                  \n"
 505             "mrsne r0, psp                  \n"
 506             "                               \n"
 507             "ldr r1, [r0, #24]              \n"
 508             "ldrb r2, [r1, #-2]             \n"
 509             "cmp r2, %0                     \n"
 510             "blt syscall_enter              \n"
 511             "cmp r2, %1                     \n"
 512             "beq syscall_exit               \n"
 513             "b vPortSVCHandler_C            \n"
 514             "                               \n"
 515             "syscall_enter:                 \n"
 516             "    mov r1, lr                 \n"
 517             "    b vSystemCallEnter         \n"
 518             "                               \n"
 519             "syscall_exit:                  \n"
 520             "    mov r1, lr                 \n"
 521             "    b vSystemCallExit          \n"
 522             "                               \n"
 523             : /* No outputs. */
 524             : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
 525             : "r0", "r1", "r2", "memory"
 526         );
 527     }
 528
 529 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 530
 531     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 532     {
 533         __asm volatile
 534         (
 535             "   .syntax unified                                 \n"
 536             "                                                   \n"
 537             "   tst lr, #4                                      \n"
 538             "   ite eq                                          \n"
 539             "   mrseq r0, msp                                   \n"
 540             "   mrsne r0, psp                                   \n"
 541             "   ldr r1, =vPortSVCHandler_C                      \n"
 542             "   bx r1                                           \n"
 543         );
 544     }
 545
 546 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 547 /*-----------------------------------------------------------*/
 548
 549 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 550 {
 551     __asm volatile
 552     (
 553         "   .syntax unified                                 \n"
 554         "                                                   \n"
 555         "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
 556         "   bx lr                                           \n" /* Return. */
 557         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
 558     );
 559 }
 560 /*-----------------------------------------------------------*/
 561
 562 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 563 {
 564     __asm volatile
 565     (
 566         "   .syntax unified                                 \n"
 567         "                                                   \n"
 568         "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
 569         "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
 570         "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
 571         "   it ne                                           \n"
 572         "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
 573         "   bx lr                                           \n" /* Return. */
 574         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
 575     );
 576 }
 577 /*-----------------------------------------------------------*/