1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: GNU GCC for AVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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18 This file is part of the FreeRTOS.org distribution.
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20 FreeRTOS.org is free software; you can redistribute it and/or modify
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21 it under the terms of the GNU General Public License as published by
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22 the Free Software Foundation; either version 2 of the License, or
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23 (at your option) any later version.
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25 FreeRTOS.org is distributed in the hope that it will be useful,
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26 but WITHOUT ANY WARRANTY; without even the implied warranty of
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27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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28 GNU General Public License for more details.
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30 You should have received a copy of the GNU General Public License
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31 along with FreeRTOS.org; if not, write to the Free Software
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32 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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34 A special exception to the GPL can be applied should you wish to distribute
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35 a combined work that includes FreeRTOS.org, without being obliged to provide
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36 the source code for any proprietary components. See the licensing section
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37 of http://www.FreeRTOS.org for full details of how and when the exception
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40 ***************************************************************************
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41 ***************************************************************************
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43 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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44 * and even write all or part of your application on your behalf. *
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45 * See http://www.OpenRTOS.com for details of the services we provide to *
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46 * expedite your project. *
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48 ***************************************************************************
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49 ***************************************************************************
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51 Please ensure to read the configuration and relevant port sections of the
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52 online documentation.
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54 http://www.FreeRTOS.org - Documentation, latest information, license and
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57 http://www.SafeRTOS.com - A version that is certified for use in safety
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60 http://www.OpenRTOS.com - Commercial support, development, porting,
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61 licensing and training services.
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68 /*-----------------------------------------------------------
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69 * Port specific definitions.
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71 * The settings in this file configure FreeRTOS correctly for the
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72 * given hardware and compiler.
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74 * These settings should not be altered.
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75 *-----------------------------------------------------------
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77 #include <avr32/io.h>
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79 #include "compiler.h"
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86 /* Type definitions. */
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87 #define portCHAR char
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88 #define portFLOAT float
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89 #define portDOUBLE double
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90 #define portLONG long
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91 #define portSHORT short
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92 #define portSTACK_TYPE unsigned portLONG
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93 #define portBASE_TYPE portLONG
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95 #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
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96 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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97 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
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99 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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101 #if( configUSE_16_BIT_TICKS == 1 )
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102 typedef unsigned portSHORT portTickType;
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103 #define portMAX_DELAY ( portTickType ) 0xffff
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105 typedef unsigned portLONG portTickType;
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106 #define portMAX_DELAY ( portTickType ) 0xffffffff
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108 /*-----------------------------------------------------------*/
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110 /* Architecture specifics. */
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111 #define portSTACK_GROWTH ( -1 )
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112 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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113 #define portBYTE_ALIGNMENT 4
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114 #define portNOP() {__asm__ __volatile__ ("nop");}
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115 /*-----------------------------------------------------------*/
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118 /*-----------------------------------------------------------*/
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120 /* INTC-specific. */
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121 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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122 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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124 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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125 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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127 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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128 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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133 * Activated if and only if configDBG is nonzero.
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134 * Prints a formatted string to stdout.
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135 * The current source file name and line number are output with a colon before
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136 * the formatted string.
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137 * A carriage return and a linefeed are appended to the output.
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138 * stdout is redirected to the USART configured by configDBG_USART.
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139 * The parameters are the same as for the standard printf function.
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140 * There is no return value.
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141 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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142 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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145 #define portDBG_TRACE(...) \
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147 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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148 printf(__VA_ARGS__);\
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149 fputs("\r\n", stdout);\
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152 #define portDBG_TRACE(...)
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156 /* Critical section management. */
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157 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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158 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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161 extern void vPortEnterCritical( void );
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162 extern void vPortExitCritical( void );
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164 #define portENTER_CRITICAL() vPortEnterCritical();
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165 #define portEXIT_CRITICAL() vPortExitCritical();
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168 /* Added as there is no such function in FreeRTOS. */
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169 extern void *pvPortRealloc( void *pv, size_t xSize );
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170 /*-----------------------------------------------------------*/
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173 /*=============================================================================================*/
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176 * Restore Context for cases other than INTi.
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178 #define portRESTORE_CONTEXT() \
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180 extern volatile unsigned portLONG ulCriticalNesting; \
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181 extern volatile void *volatile pxCurrentTCB; \
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183 __asm__ __volatile__ ( \
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184 /* Set SP to point to new stack */ \
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185 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
186 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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187 "ld.w r0, r8[0] \n\t"\
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188 "ld.w sp, r0[0] \n\t"\
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190 /* Restore ulCriticalNesting variable */ \
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191 "ld.w r0, sp++ \n\t"\
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192 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
193 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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194 "st.w r8[0], r0 \n\t"\
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196 /* Restore R0..R7 */ \
\r
197 "ldm sp++, r0-r7 \n\t"\
\r
198 /* R0-R7 should not be used below this line */ \
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199 /* Skip PC and SR (will do it at the end) */ \
\r
200 "sub sp, -2*4 \n\t"\
\r
201 /* Restore R8..R12 and LR */ \
\r
202 "ldm sp++, r8-r12, lr \n\t"\
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204 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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205 "mtsr %[SR], r0 \n\t"\
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207 "ld.w r0, sp[-9*4] \n\t"\
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209 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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211 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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212 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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213 [SR] "i" (AVR32_SR) \
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219 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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220 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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222 * Had to make different versions because registers saved on the system stack
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223 * are not the same between INT0..3 exceptions and the scall exception.
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226 // Task context stack layout:
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243 // ulCriticalNesting
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244 // (*) automatically done for INT0..INT3, but not for SCALL
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247 * The ISR used for the scheduler tick depends on whether the cooperative or
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248 * the preemptive scheduler is being used.
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250 #if configUSE_PREEMPTION == 0
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253 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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255 #define portSAVE_CONTEXT_OS_INT() \
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257 /* Save R0..R7 */ \
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258 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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260 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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261 /* there is also no context save. */ \
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265 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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267 #define portRESTORE_CONTEXT_OS_INT() \
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269 __asm__ __volatile__ ( \
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270 /* Restore R0..R7 */ \
\r
271 "ldm sp++, r0-r7\n\t" \
\r
273 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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274 /* there is also no context restore. */ \
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282 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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284 #define portSAVE_CONTEXT_OS_INT() \
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286 extern volatile unsigned portLONG ulCriticalNesting; \
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287 extern volatile void *volatile pxCurrentTCB; \
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289 /* When we come here */ \
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290 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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292 __asm__ __volatile__ ( \
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293 /* Save R0..R7 */ \
\r
294 "stm --sp, r0-r7 \n\t"\
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296 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
297 "mov r8, LO(%[ulCriticalNesting])\n\t" \
\r
298 "orh r8, HI(%[ulCriticalNesting])\n\t" \
\r
299 "ld.w r0, r8[0] \n\t"\
\r
300 "st.w --sp, r0 \n\t"\
\r
302 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
303 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
304 /* level and allow other lower interrupt level to occur). */ \
\r
305 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
306 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
307 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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308 /* will just be restoring the interrupt handler, no way!!! */ \
\r
309 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
310 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
311 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
312 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
313 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
315 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
316 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
\r
317 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
\r
318 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
\r
319 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
\r
320 "mov r8, LO(%[pxCurrentTCB])\n\t" \
\r
321 "orh r8, HI(%[pxCurrentTCB])\n\t" \
\r
322 "ld.w r0, r8[0]\n\t" \
\r
323 "st.w r0[0], sp\n" \
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325 "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
327 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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328 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
329 [LINE] "i" (__LINE__) \
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334 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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336 #define portRESTORE_CONTEXT_OS_INT() \
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338 extern volatile unsigned portLONG ulCriticalNesting; \
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339 extern volatile void *volatile pxCurrentTCB; \
\r
341 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
342 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
343 /* level and allow other lower interrupt level to occur). */ \
\r
344 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
345 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
346 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
347 /* will just be restoring the interrupt handler, no way!!! */ \
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348 __asm__ __volatile__ ( \
\r
349 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
350 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
351 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
352 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
\r
354 : [LINE] "i" (__LINE__) \
\r
358 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
\r
359 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
360 portENTER_CRITICAL(); \
\r
361 vTaskSwitchContext(); \
\r
362 portEXIT_CRITICAL(); \
\r
364 /* Restore all registers */ \
\r
366 __asm__ __volatile__ ( \
\r
367 /* Set SP to point to new stack */ \
\r
368 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
369 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
370 "ld.w r0, r8[0] \n\t"\
\r
371 "ld.w sp, r0[0] \n"\
\r
373 "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
375 /* Restore ulCriticalNesting variable */ \
\r
376 "ld.w r0, sp++ \n\t" \
\r
377 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
378 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
379 "st.w r8[0], r0 \n\t"\
\r
381 /* Restore R0..R7 */ \
\r
382 "ldm sp++, r0-r7 \n\t"\
\r
384 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
387 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
388 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
389 [LINE] "i" (__LINE__) \
\r
397 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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399 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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402 #define portSAVE_CONTEXT_SCALL() \
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404 extern volatile unsigned portLONG ulCriticalNesting; \
\r
405 extern volatile void *volatile pxCurrentTCB; \
\r
407 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
408 /* If SR[M2:M0] == 001 */ \
\r
409 /* PC and SR are on the stack. */ \
\r
410 /* Else (other modes) */ \
\r
411 /* Nothing on the stack. */ \
\r
413 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
414 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
415 /* in an interrupt|exception handler. */ \
\r
417 __asm__ __volatile__ ( \
\r
418 /* in order to save R0-R7 */ \
\r
419 "sub sp, 6*4 \n\t"\
\r
420 /* Save R0..R7 */ \
\r
421 "stm --sp, r0-r7 \n\t"\
\r
423 /* in order to save R8-R12 and LR */ \
\r
424 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
425 "sub r7, sp,-16*4 \n\t"\
\r
426 /* Copy PC and SR in other places in the stack. */ \
\r
427 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
428 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
429 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
430 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
432 /* Save R8..R12 and LR on the stack. */ \
\r
433 "stm --r7, r8-r12, lr \n\t"\
\r
435 /* Arriving here we have the following stack organizations: */ \
\r
436 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
438 /* Now we can finalize the save. */ \
\r
440 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
441 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
442 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
443 "ld.w r0, r8[0] \n\t"\
\r
446 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
449 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
450 /* pxCurrentTCB). */ \
\r
451 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
452 /* critical section because it is a global structure. */ \
\r
453 portENTER_CRITICAL(); \
\r
455 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
456 __asm__ __volatile__ ( \
\r
457 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
458 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
459 "ld.w r0, r8[0] \n\t"\
\r
462 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
467 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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469 #define portRESTORE_CONTEXT_SCALL() \
\r
471 extern volatile unsigned portLONG ulCriticalNesting; \
\r
472 extern volatile void *volatile pxCurrentTCB; \
\r
474 /* Restore all registers */ \
\r
476 /* Set SP to point to new stack */ \
\r
477 __asm__ __volatile__ ( \
\r
478 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
479 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
480 "ld.w r0, r8[0] \n\t"\
\r
483 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
486 /* Leave pxCurrentTCB variable access critical section */ \
\r
487 portEXIT_CRITICAL(); \
\r
489 __asm__ __volatile__ ( \
\r
490 /* Restore ulCriticalNesting variable */ \
\r
491 "ld.w r0, sp++ \n\t"\
\r
492 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
493 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
494 "st.w r8[0], r0 \n\t"\
\r
496 /* skip PC and SR */ \
\r
497 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
498 "sub r7, sp, -10*4 \n\t"\
\r
499 /* Restore r8-r12 and LR */ \
\r
500 "ldm r7++, r8-r12, lr \n\t"\
\r
502 /* RETS will take care of the extra PC and SR restore. */ \
\r
503 /* So, we have to prepare the stack for this. */ \
\r
504 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
505 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
506 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
507 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
509 /* Restore R0..R7 */ \
\r
510 "ldm sp++, r0-r7 \n\t"\
\r
512 "sub sp, -6*4 \n\t"\
\r
516 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
522 * The ISR used depends on whether the cooperative or
\r
523 * the preemptive scheduler is being used.
\r
525 #if configUSE_PREEMPTION == 0
\r
528 * ISR entry and exit macros. These are only required if a task switch
\r
529 * is required from the ISR.
\r
531 #define portENTER_SWITCHING_ISR() \
\r
533 /* Save R0..R7 */ \
\r
534 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
536 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
537 /* there is also no context save. */ \
\r
541 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
543 #define portEXIT_SWITCHING_ISR() \
\r
545 __asm__ __volatile__ ( \
\r
546 /* Restore R0..R7 */ \
\r
547 "ldm sp++, r0-r7 \n\t"\
\r
549 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
550 /* there is also no context restore. */ \
\r
558 * ISR entry and exit macros. These are only required if a task switch
\r
559 * is required from the ISR.
\r
561 #define portENTER_SWITCHING_ISR() \
\r
563 extern volatile unsigned portLONG ulCriticalNesting; \
\r
564 extern volatile void *volatile pxCurrentTCB; \
\r
566 /* When we come here */ \
\r
567 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
569 __asm__ __volatile__ ( \
\r
570 /* Save R0..R7 */ \
\r
571 "stm --sp, r0-r7 \n\t"\
\r
573 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
574 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
575 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
576 "ld.w r0, r8[0] \n\t"\
\r
577 "st.w --sp, r0 \n\t"\
\r
579 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
580 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
581 /* level and allow other lower interrupt level to occur). */ \
\r
582 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
583 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
584 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
585 /* will just be restoring the interrupt handler, no way!!! */ \
\r
586 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
587 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
588 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
589 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
590 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
592 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
593 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
594 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
595 "ld.w r0, r8[0] \n\t"\
\r
596 "st.w r0[0], sp \n"\
\r
598 "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
600 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
601 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
602 [LINE] "i" (__LINE__) \
\r
607 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
609 #define portEXIT_SWITCHING_ISR() \
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611 extern volatile unsigned portLONG ulCriticalNesting; \
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612 extern volatile void *volatile pxCurrentTCB; \
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614 __asm__ __volatile__ ( \
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615 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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616 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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617 /* level and allow other lower interrupt level to occur). */ \
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618 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
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619 /* did not previously save SP in its TCB. */ \
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620 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
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621 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
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622 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
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623 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
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625 /* If a switch is required then we just need to call */ \
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626 /* vTaskSwitchContext() as the context has already been */ \
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628 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
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629 "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
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631 : [LINE] "i" (__LINE__) \
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634 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
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635 portENTER_CRITICAL(); \
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636 vTaskSwitchContext(); \
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637 portEXIT_CRITICAL(); \
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639 __asm__ __volatile__ ( \
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640 "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
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641 /* Restore the context of which ever task is now the highest */ \
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642 /* priority that is ready to run. */ \
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644 /* Restore all registers */ \
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646 /* Set SP to point to new stack */ \
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647 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
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648 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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649 "ld.w r0, r8[0] \n\t"\
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650 "ld.w sp, r0[0] \n"\
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652 "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
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654 /* Restore ulCriticalNesting variable */ \
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655 "ld.w r0, sp++ \n\t"\
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656 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
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657 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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658 "st.w r8[0], r0 \n\t"\
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660 /* Restore R0..R7 */ \
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661 "ldm sp++, r0-r7 \n\t"\
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663 /* Now, the stack should be R8..R12, LR, PC and SR */ \
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666 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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667 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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668 [LINE] "i" (__LINE__) \
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675 #define portYIELD() {__asm__ __volatile__ ("scall");}
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677 /* Task function macros as described on the FreeRTOS.org WEB site. */
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678 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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679 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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685 #endif /* PORTMACRO_H */
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