begriffs open source - freertos/blob - portable/GCC/ARM7_AT91FR40008/portmacro.h

   1 /*
   2  * FreeRTOS Kernel V10.4.3
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   6  * this software and associated documentation files (the "Software"), to deal in
   7  * the Software without restriction, including without limitation the rights to
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
   9  * the Software, and to permit persons to whom the Software is furnished to do so,
  10  * subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * https://www.FreeRTOS.org
  23  * https://github.com/FreeRTOS
  24  *
  25  * 1 tab == 4 spaces!
  26  */
  27
  28 /*
  29         Changes from V3.2.3
  30
  31         + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
  32
  33         Changes from V3.2.4
  34
  35         + Removed the use of the %0 parameter within the assembler macros and
  36           replaced them with hard coded registers.  This will ensure the
  37           assembler does not select the link register as the temp register as
  38           was occasionally happening previously.
  39
  40         + The assembler statements are now included in a single asm block rather
  41           than each line having its own asm block.
  42
  43         Changes from V4.5.0
  44
  45         + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
  46           and replaced them with portYIELD_FROM_ISR() macro.  Application code
  47           should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
  48           macros as per the V4.5.1 demo code.
  49 */
  50
  51 #ifndef PORTMACRO_H
  52 #define PORTMACRO_H
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 /*-----------------------------------------------------------
  59  * Port specific definitions.
  60  *
  61  * The settings in this file configure FreeRTOS correctly for the
  62  * given hardware and compiler.
  63  *
  64  * These settings should not be altered.
  65  *-----------------------------------------------------------
  66  */
  67
  68 /* Type definitions. */
  69 #define portCHAR                char
  70 #define portFLOAT               float
  71 #define portDOUBLE              double
  72 #define portLONG                long
  73 #define portSHORT               short
  74 #define portSTACK_TYPE  uint32_t
  75 #define portBASE_TYPE   long
  76
  77 typedef portSTACK_TYPE StackType_t;
  78 typedef long BaseType_t;
  79 typedef unsigned long UBaseType_t;
  80
  81 #if( configUSE_16_BIT_TICKS == 1 )
  82         typedef uint16_t TickType_t;
  83         #define portMAX_DELAY ( TickType_t ) 0xffff
  84 #else
  85         typedef uint32_t TickType_t;
  86         #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
  87 #endif
  88 /*-----------------------------------------------------------*/
  89
  90 /* Hardware specifics. */
  91 #define portSTACK_GROWTH                        ( -1 )
  92 #define portTICK_PERIOD_MS                      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
  93 #define portBYTE_ALIGNMENT                      8
  94 #define portYIELD()                                     asm volatile ( "SWI 0" )
  95 #define portNOP()                                       asm volatile ( "NOP" )
  96
  97 /*
  98  * These define the timer to use for generating the tick interrupt.
  99  * They are put in this file so they can be shared between "port.c"
 100  * and "portisr.c".
 101  */
 102 #define portTIMER_REG_BASE_PTR          AT91C_BASE_TC0
 103 #define portTIMER_CLK_ENABLE_BIT        AT91C_PS_TC0
 104 #define portTIMER_AIC_CHANNEL           ( ( uint32_t ) 4 )
 105 /*-----------------------------------------------------------*/
 106
 107 /* Task utilities. */
 108
 109 /*
 110  * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
 111  * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
 112  * are included here for efficiency.  An attempt to call one from
 113  * THUMB mode code will result in a compile time error.
 114  */
 115
 116 #define portRESTORE_CONTEXT()                                                                                   \
 117 {                                                                                                                                               \
 118 extern volatile void * volatile pxCurrentTCB;                                                   \
 119 extern volatile uint32_t ulCriticalNesting;                                     \
 120                                                                                                                                                 \
 121         /* Set the LR to the task stack. */                                                                     \
 122         asm volatile (                                                                                                          \
 123         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \
 124         "LDR            R0, [R0]                                                                                \n\t"   \
 125         "LDR            LR, [R0]                                                                                \n\t"   \
 126                                                                                                                                                 \
 127         /* The critical nesting depth is the first item on the stack. */        \
 128         /* Load it into the ulCriticalNesting variable. */                                      \
 129         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \
 130         "LDMFD  LR!, {R1}                                                                                       \n\t"   \
 131         "STR            R1, [R0]                                                                                \n\t"   \
 132                                                                                                                                                 \
 133         /* Get the SPSR from the stack. */                                                                      \
 134         "LDMFD  LR!, {R0}                                                                                       \n\t"   \
 135         "MSR            SPSR, R0                                                                                \n\t"   \
 136                                                                                                                                                 \
 137         /* Restore all system mode registers for the task. */                           \
 138         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \
 139         "NOP                                                                                                            \n\t"   \
 140                                                                                                                                                 \
 141         /* Restore the return address. */                                                                       \
 142         "LDR            LR, [LR, #+60]                                                                  \n\t"   \
 143                                                                                                                                                 \
 144         /* And return - correcting the offset in the LR to obtain the */        \
 145         /* correct address. */                                                                                          \
 146         "SUBS   PC, LR, #4                                                                                      \n\t"   \
 147         );                                                                                                                                      \
 148         ( void ) ulCriticalNesting;                                                                                     \
 149         ( void ) pxCurrentTCB;                                                                                          \
 150 }
 151 /*-----------------------------------------------------------*/
 152
 153 #define portSAVE_CONTEXT()                                                                                              \
 154 {                                                                                                                                               \
 155 extern volatile void * volatile pxCurrentTCB;                                                   \
 156 extern volatile uint32_t ulCriticalNesting;                                     \
 157                                                                                                                                                 \
 158         /* Push R0 as we are going to use the register. */                                      \
 159         asm volatile (                                                                                                          \
 160         "STMDB  SP!, {R0}                                                                                       \n\t"   \
 161                                                                                                                                                 \
 162         /* Set R0 to point to the task stack pointer. */                                        \
 163         "STMDB  SP,{SP}^                                                                                        \n\t"   \
 164         "NOP                                                                                                            \n\t"   \
 165         "SUB    SP, SP, #4                                                                                      \n\t"   \
 166         "LDMIA  SP!,{R0}                                                                                        \n\t"   \
 167                                                                                                                                                 \
 168         /* Push the return address onto the stack. */                                           \
 169         "STMDB  R0!, {LR}                                                                                       \n\t"   \
 170                                                                                                                                                 \
 171         /* Now we have saved LR we can use it instead of R0. */                         \
 172         "MOV    LR, R0                                                                                          \n\t"   \
 173                                                                                                                                                 \
 174         /* Pop R0 so we can save it onto the system mode stack. */                      \
 175         "LDMIA  SP!, {R0}                                                                                       \n\t"   \
 176                                                                                                                                                 \
 177         /* Push all the system mode registers onto the task stack. */           \
 178         "STMDB  LR,{R0-LR}^                                                                                     \n\t"   \
 179         "NOP                                                                                                            \n\t"   \
 180         "SUB    LR, LR, #60                                                                                     \n\t"   \
 181                                                                                                                                                 \
 182         /* Push the SPSR onto the task stack. */                                                        \
 183         "MRS    R0, SPSR                                                                                        \n\t"   \
 184         "STMDB  LR!, {R0}                                                                                       \n\t"   \
 185                                                                                                                                                 \
 186         "LDR    R0, =ulCriticalNesting                                                          \n\t"   \
 187         "LDR    R0, [R0]                                                                                        \n\t"   \
 188         "STMDB  LR!, {R0}                                                                                       \n\t"   \
 189                                                                                                                                                 \
 190         /* Store the new top of stack for the task. */                                          \
 191         "LDR    R0, =pxCurrentTCB                                                                       \n\t"   \
 192         "LDR    R0, [R0]                                                                                        \n\t"   \
 193         "STR    LR, [R0]                                                                                        \n\t"   \
 194         );                                                                                                                                      \
 195         ( void ) ulCriticalNesting;                                                                                     \
 196         ( void ) pxCurrentTCB;                                                                                          \
 197 }
 198
 199 #define portYIELD_FROM_ISR() vTaskSwitchContext()
 200
 201 /* Critical section handling. */
 202
 203 /*
 204  * The interrupt management utilities can only be called from ARM mode.  When
 205  * THUMB_INTERWORK is defined the utilities are defined as functions in
 206  * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
 207  * defined then the utilities are defined as macros here - as per other ports.
 208  */
 209
 210 #ifdef THUMB_INTERWORK
 211
 212         extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
 213         extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
 214
 215         #define portDISABLE_INTERRUPTS()        vPortDisableInterruptsFromThumb()
 216         #define portENABLE_INTERRUPTS()         vPortEnableInterruptsFromThumb()
 217
 218 #else
 219
 220         #define portDISABLE_INTERRUPTS()                                                                                        \
 221                 asm volatile (                                                                                                                  \
 222                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
 223                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
 224                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                    */      \
 225                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
 226                         "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
 227
 228         #define portENABLE_INTERRUPTS()                                                                                         \
 229                 asm volatile (                                                                                                                  \
 230                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
 231                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
 232                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \
 233                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
 234                         "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
 235
 236 #endif /* THUMB_INTERWORK */
 237
 238 extern void vPortEnterCritical( void );
 239 extern void vPortExitCritical( void );
 240
 241 #define portENTER_CRITICAL()            vPortEnterCritical();
 242 #define portEXIT_CRITICAL()                     vPortExitCritical();
 243
 244 /*-----------------------------------------------------------*/
 245
 246 /* Task function macros as described on the FreeRTOS.org WEB site. */
 247 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 248 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 249
 250 #ifdef __cplusplus
 251 }
 252 #endif
 253
 254 #endif /* PORTMACRO_H */
 255