begriffs open source - freertos/blob - portable/GCC/RX600v2/port.c

   1 /*
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28
  29 /*-----------------------------------------------------------
  30 * Implementation of functions defined in portable.h for the SH2A port.
  31 *----------------------------------------------------------*/
  32
  33 /* Scheduler includes. */
  34 #include "FreeRTOS.h"
  35 #include "task.h"
  36
  37 /* Library includes. */
  38 #include "string.h"
  39
  40 /* Hardware specifics. */
  41 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
  42
  43     #include "platform.h"
  44
  45 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
  46
  47     #include "iodefine.h"
  48
  49 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
  50
  51 /*-----------------------------------------------------------*/
  52
  53 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
  54  * PSW is set with U and I set, and PM and IPL clear. */
  55 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
  56 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
  57
  58 /* These macros allow a critical section to be added around the call to
  59  * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
  60  * priority - ie a known priority.  Therefore these local macros are a slight
  61  * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
  62  * which would require the old IPL to be read first and stored in a local variable. */
  63 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR()      __asm volatile ( "MVTIPL    %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
  64 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL    %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
  65
  66 /*-----------------------------------------------------------*/
  67
  68 /*
  69  * Function to start the first task executing - written in asm code as direct
  70  * access to registers is required.
  71  */
  72 static void prvStartFirstTask( void ) __attribute__( ( naked ) );
  73
  74 /*
  75  * Software interrupt handler.  Performs the actual context switch (saving and
  76  * restoring of registers).  Written in asm code as direct register access is
  77  * required.
  78  */
  79 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
  80     R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
  81     R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
  82 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
  83     void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
  84 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
  85
  86 /*
  87  * The tick ISR handler.  The peripheral used is configured by the application
  88  * via a hook/callback function.
  89  */
  90 #if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
  91
  92     R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
  93     R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
  94
  95 #else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
  96
  97     void vTickISR( void ) __attribute__( ( interrupt ) );
  98
  99 #endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
 100 /*-----------------------------------------------------------*/
 101
 102 extern void * pxCurrentTCB;
 103
 104 /*-----------------------------------------------------------*/
 105
 106 /*
 107  * See header file for description.
 108  */
 109 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
 110                                      TaskFunction_t pxCode,
 111                                      void * pvParameters )
 112 {
 113     /* R0 is not included as it is the stack pointer. */
 114
 115     *pxTopOfStack = 0x00;
 116     pxTopOfStack--;
 117     *pxTopOfStack = portINITIAL_PSW;
 118     pxTopOfStack--;
 119     *pxTopOfStack = ( StackType_t ) pxCode;
 120
 121     /* When debugging it can be useful if every register is set to a known
 122      * value.  Otherwise code space can be saved by just setting the registers
 123      * that need to be set. */
 124     #ifdef USE_FULL_REGISTER_INITIALISATION
 125     {
 126         pxTopOfStack--;
 127         *pxTopOfStack = 0xffffffff; /* r15. */
 128         pxTopOfStack--;
 129         *pxTopOfStack = 0xeeeeeeee;
 130         pxTopOfStack--;
 131         *pxTopOfStack = 0xdddddddd;
 132         pxTopOfStack--;
 133         *pxTopOfStack = 0xcccccccc;
 134         pxTopOfStack--;
 135         *pxTopOfStack = 0xbbbbbbbb;
 136         pxTopOfStack--;
 137         *pxTopOfStack = 0xaaaaaaaa;
 138         pxTopOfStack--;
 139         *pxTopOfStack = 0x99999999;
 140         pxTopOfStack--;
 141         *pxTopOfStack = 0x88888888;
 142         pxTopOfStack--;
 143         *pxTopOfStack = 0x77777777;
 144         pxTopOfStack--;
 145         *pxTopOfStack = 0x66666666;
 146         pxTopOfStack--;
 147         *pxTopOfStack = 0x55555555;
 148         pxTopOfStack--;
 149         *pxTopOfStack = 0x44444444;
 150         pxTopOfStack--;
 151         *pxTopOfStack = 0x33333333;
 152         pxTopOfStack--;
 153         *pxTopOfStack = 0x22222222;
 154         pxTopOfStack--;
 155     }
 156     #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
 157     {
 158         pxTopOfStack -= 15;
 159     }
 160     #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
 161
 162     *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
 163     pxTopOfStack--;
 164     *pxTopOfStack = portINITIAL_FPSW;
 165     pxTopOfStack--;
 166     *pxTopOfStack = 0x11111111; /* Accumulator 0. */
 167     pxTopOfStack--;
 168     *pxTopOfStack = 0x22222222; /* Accumulator 0. */
 169     pxTopOfStack--;
 170     *pxTopOfStack = 0x33333333; /* Accumulator 0. */
 171     pxTopOfStack--;
 172     *pxTopOfStack = 0x44444444; /* Accumulator 1. */
 173     pxTopOfStack--;
 174     *pxTopOfStack = 0x55555555; /* Accumulator 1. */
 175     pxTopOfStack--;
 176     *pxTopOfStack = 0x66666666; /* Accumulator 1. */
 177
 178     return pxTopOfStack;
 179 }
 180 /*-----------------------------------------------------------*/
 181
 182 BaseType_t xPortStartScheduler( void )
 183 {
 184     extern void vApplicationSetupTimerInterrupt( void );
 185
 186     /* Use pxCurrentTCB just so it does not get optimised away. */
 187     if( pxCurrentTCB != NULL )
 188     {
 189         /* Call an application function to set up the timer that will generate the
 190          * tick interrupt.  This way the application can decide which peripheral to
 191          * use.  A demo application is provided to show a suitable example. */
 192         vApplicationSetupTimerInterrupt();
 193
 194         /* Enable the software interrupt. */
 195         _IEN( _ICU_SWINT ) = 1;
 196
 197         /* Ensure the software interrupt is clear. */
 198         _IR( _ICU_SWINT ) = 0;
 199
 200         /* Ensure the software interrupt is set to the kernel priority. */
 201         _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
 202
 203         /* Start the first task. */
 204         prvStartFirstTask();
 205     }
 206
 207     /* Should not get here. */
 208     return pdFAIL;
 209 }
 210 /*-----------------------------------------------------------*/
 211
 212 void vPortEndScheduler( void )
 213 {
 214     /* Not implemented in ports where there is nothing to return to.
 215      * Artificially force an assert. */
 216     configASSERT( pxCurrentTCB == NULL );
 217 }
 218 /*-----------------------------------------------------------*/
 219
 220 static void prvStartFirstTask( void )
 221 {
 222     __asm volatile
 223     (
 224
 225         /* When starting the scheduler there is nothing that needs moving to the
 226          * interrupt stack because the function is not called from an interrupt.
 227          * Just ensure the current stack is the user stack. */
 228         "SETPSW     U                       \n" \
 229
 230
 231         /* Obtain the location of the stack associated with which ever task
 232          * pxCurrentTCB is currently pointing to. */
 233         "MOV.L      #_pxCurrentTCB, R15     \n" \
 234         "MOV.L      [R15], R15              \n" \
 235         "MOV.L      [R15], R0               \n" \
 236
 237
 238         /* Restore the registers from the stack of the task pointed to by
 239          * pxCurrentTCB. */
 240         "POP        R15                     \n" \
 241
 242         /* Accumulator low 32 bits. */
 243         "MVTACLO    R15, A0                 \n" \
 244         "POP        R15                     \n" \
 245
 246         /* Accumulator high 32 bits. */
 247         "MVTACHI    R15, A0                 \n" \
 248         "POP        R15                     \n" \
 249
 250         /* Accumulator guard. */
 251         "MVTACGU    R15, A0                 \n" \
 252         "POP        R15                     \n" \
 253
 254         /* Accumulator low 32 bits. */
 255         "MVTACLO    R15, A1                 \n" \
 256         "POP        R15                     \n" \
 257
 258         /* Accumulator high 32 bits. */
 259         "MVTACHI    R15, A1                 \n" \
 260         "POP        R15                     \n" \
 261
 262         /* Accumulator guard. */
 263         "MVTACGU    R15, A1                 \n" \
 264         "POP        R15                     \n" \
 265
 266         /* Floating point status word. */
 267         "MVTC       R15, FPSW               \n" \
 268
 269         /* R1 to R15 - R0 is not included as it is the SP. */
 270         "POPM       R1-R15                  \n" \
 271
 272         /* This pops the remaining registers. */
 273         "RTE                                \n" \
 274         "NOP                                \n" \
 275         "NOP                                \n"
 276     );
 277 }
 278 /*-----------------------------------------------------------*/
 279
 280 void vSoftwareInterruptISR( void )
 281 {
 282     __asm volatile
 283     (
 284         /* Re-enable interrupts. */
 285         "SETPSW     I                           \n" \
 286
 287
 288         /* Move the data that was automatically pushed onto the interrupt stack when
 289          * the interrupt occurred from the interrupt stack to the user stack.
 290          *
 291          * R15 is saved before it is clobbered. */
 292         "PUSH.L     R15                         \n" \
 293
 294         /* Read the user stack pointer. */
 295         "MVFC       USP, R15                    \n" \
 296
 297         /* Move the address down to the data being moved. */
 298         "SUB        #12, R15                    \n" \
 299         "MVTC       R15, USP                    \n" \
 300
 301         /* Copy the data across, R15, then PC, then PSW. */
 302         "MOV.L      [ R0 ], [ R15 ]             \n" \
 303         "MOV.L      4[ R0 ], 4[ R15 ]           \n" \
 304         "MOV.L      8[ R0 ], 8[ R15 ]           \n" \
 305
 306         /* Move the interrupt stack pointer to its new correct position. */
 307         "ADD        #12, R0                     \n" \
 308
 309         /* All the rest of the registers are saved directly to the user stack. */
 310         "SETPSW     U                           \n" \
 311
 312         /* Save the rest of the general registers (R15 has been saved already). */
 313         "PUSHM      R1-R14                      \n" \
 314
 315         /* Save the FPSW and accumulator. */
 316         "MVFC       FPSW, R15                   \n" \
 317         "PUSH.L     R15                         \n" \
 318         "MVFACGU    #0, A1, R15                 \n" \
 319         "PUSH.L     R15                         \n" \
 320         "MVFACHI    #0, A1, R15                 \n" \
 321         "PUSH.L     R15                         \n" \
 322         /* Low order word. */
 323         "MVFACLO    #0, A1, R15                 \n" \
 324         "PUSH.L     R15                         \n" \
 325         "MVFACGU    #0, A0, R15                 \n" \
 326         "PUSH.L     R15                         \n" \
 327         "MVFACHI    #0, A0, R15                 \n" \
 328         "PUSH.L     R15                         \n" \
 329         /* Low order word. */
 330         "MVFACLO    #0, A0, R15                 \n" \
 331         "PUSH.L     R15                         \n" \
 332
 333         /* Save the stack pointer to the TCB. */
 334         "MOV.L      #_pxCurrentTCB, R15         \n" \
 335         "MOV.L      [ R15 ], R15                \n" \
 336         "MOV.L      R0, [ R15 ]                 \n" \
 337
 338
 339         /* Ensure the interrupt mask is set to the syscall priority while the kernel
 340          * structures are being accessed. */
 341         "MVTIPL     %0                          \n" \
 342
 343         /* Select the next task to run. */
 344         "BSR.A      _vTaskSwitchContext         \n" \
 345
 346         /* Reset the interrupt mask as no more data structure access is required. */
 347         "MVTIPL     %1                          \n" \
 348
 349
 350         /* Load the stack pointer of the task that is now selected as the Running
 351          * state task from its TCB. */
 352         "MOV.L      #_pxCurrentTCB,R15          \n" \
 353         "MOV.L      [ R15 ], R15                \n" \
 354         "MOV.L      [ R15 ], R0                 \n" \
 355
 356
 357         /* Restore the context of the new task.  The PSW (Program Status Word) and
 358          * PC will be popped by the RTE instruction. */
 359         "POP        R15                         \n" \
 360
 361         /* Accumulator low 32 bits. */
 362         "MVTACLO    R15, A0                     \n" \
 363         "POP        R15                         \n" \
 364
 365         /* Accumulator high 32 bits. */
 366         "MVTACHI    R15, A0                     \n" \
 367         "POP        R15                         \n" \
 368
 369         /* Accumulator guard. */
 370         "MVTACGU    R15, A0                     \n" \
 371         "POP        R15                         \n" \
 372
 373         /* Accumulator low 32 bits. */
 374         "MVTACLO    R15, A1                     \n" \
 375         "POP        R15                         \n" \
 376
 377         /* Accumulator high 32 bits. */
 378         "MVTACHI    R15, A1                     \n" \
 379         "POP        R15                         \n" \
 380
 381         /* Accumulator guard. */
 382         "MVTACGU    R15, A1                     \n" \
 383         "POP        R15                         \n" \
 384         "MVTC       R15, FPSW                   \n" \
 385         "POPM       R1-R15                      \n" \
 386         "RTE                                    \n" \
 387         "NOP                                    \n" \
 388         "NOP                                      "
 389         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
 390     );
 391 }
 392 /*-----------------------------------------------------------*/
 393
 394 void vTickISR( void )
 395 {
 396     /* Re-enabled interrupts. */
 397     __asm volatile ( "SETPSW I" );
 398
 399     /* Increment the tick, and perform any processing the new tick value
 400      * necessitates.  Ensure IPL is at the max syscall value first. */
 401     portMASK_INTERRUPTS_FROM_KERNEL_ISR();
 402     {
 403         if( xTaskIncrementTick() != pdFALSE )
 404         {
 405             taskYIELD();
 406         }
 407     }
 408     portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
 409 }
 410 /*-----------------------------------------------------------*/
 411
 412 uint32_t ulPortGetIPL( void )
 413 {
 414     __asm volatile
 415     (
 416         "MVFC   PSW, R1         \n" \
 417         "SHLR   #24, R1         \n" \
 418         "RTS                      "
 419     );
 420
 421     /* This will never get executed, but keeps the compiler from complaining. */
 422     return 0;
 423 }
 424 /*-----------------------------------------------------------*/
 425
 426 void vPortSetIPL( uint32_t ulNewIPL )
 427 {
 428     /* Avoid compiler warning about unreferenced parameter. */
 429     ( void ) ulNewIPL;
 430
 431     __asm volatile
 432     (
 433         "PUSH   R5              \n" \
 434         "MVFC   PSW, R5         \n" \
 435         "SHLL   #24, R1         \n" \
 436         "AND    #-0F000001H, R5 \n" \
 437         "OR     R1, R5          \n" \
 438         "MVTC   R5, PSW         \n" \
 439         "POP    R5              \n" \
 440         "RTS                      "
 441     );
 442 }