begriffs open source - freertos/blob - portable/IAR/ARM_CM33/non_secure/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.3.1\r
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  */\r
  26 \r
  27 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  28  * all the API functions to use the MPU wrappers. That should only be done when\r
  29  * task.h is included from an application file. */\r
  30 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  31 \r
  32 /* Scheduler includes. */\r
  33 #include "FreeRTOS.h"\r
  34 #include "task.h"\r
  35 \r
  36 /* MPU wrappers includes. */\r
  37 #include "mpu_wrappers.h"\r
  38 \r
  39 /* Portasm includes. */\r
  40 #include "portasm.h"\r
  41 \r
  42 #if( configENABLE_TRUSTZONE == 1 )\r
  43         /* Secure components includes. */\r
  44         #include "secure_context.h"\r
  45         #include "secure_init.h"\r
  46 #endif /* configENABLE_TRUSTZONE */\r
  47 \r
  48 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  49 \r
  50 /**\r
  51  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
  52  * i.e. the processor boots as secure and never jumps to the non-secure side.\r
  53  * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
  54  * on the secure side. The following are the valid configuration seetings:\r
  55  *\r
  56  * 1. Run FreeRTOS on the Secure Side:\r
  57  *              configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
  58  *\r
  59  * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
  60  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
  61  *\r
  62  * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
  63  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
  64  */\r
  65 #if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
  66         #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
  67 #endif\r
  68 /*-----------------------------------------------------------*/\r
  69 \r
  70 /**\r
  71  * @brief Constants required to manipulate the NVIC.\r
  72  */\r
  73 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  74 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  75 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  76 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  77 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  78 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  79 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  80 #define portMIN_INTERRUPT_PRIORITY                      ( 255UL )\r
  81 #define portNVIC_PENDSV_PRI                                     ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
  82 #define portNVIC_SYSTICK_PRI                            ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
  83 #ifndef configSYSTICK_CLOCK_HZ\r
  84         #define configSYSTICK_CLOCK_HZ                  configCPU_CLOCK_HZ\r
  85         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  86         #define portNVIC_SYSTICK_CLK_BIT                ( 1UL << 2UL )\r
  87 #else\r
  88         /* The way the SysTick is clocked is not modified in case it is not the\r
  89          * same a the core. */\r
  90         #define portNVIC_SYSTICK_CLK_BIT                ( 0 )\r
  91 #endif\r
  92 /*-----------------------------------------------------------*/\r
  93 \r
  94 /**\r
  95  * @brief Constants required to manipulate the SCB.\r
  96  */\r
  97 #define portSCB_SYS_HANDLER_CTRL_STATE_REG      ( * ( volatile uint32_t * ) 0xe000ed24 )\r
  98 #define portSCB_MEM_FAULT_ENABLE_BIT            ( 1UL << 16UL )\r
  99 /*-----------------------------------------------------------*/\r
 100 \r
 101 /**\r
 102  * @brief Constants required to manipulate the FPU.\r
 103  */\r
 104 #define portCPACR                                                       ( ( volatile uint32_t * ) 0xe000ed88 )  /* Coprocessor Access Control Register. */\r
 105 #define portCPACR_CP10_VALUE                            ( 3UL )\r
 106 #define portCPACR_CP11_VALUE                            portCPACR_CP10_VALUE\r
 107 #define portCPACR_CP10_POS                                      ( 20UL )\r
 108 #define portCPACR_CP11_POS                                      ( 22UL )\r
 109 \r
 110 #define portFPCCR                                                       ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
 111 #define portFPCCR_ASPEN_POS                                     ( 31UL )\r
 112 #define portFPCCR_ASPEN_MASK                            ( 1UL << portFPCCR_ASPEN_POS )\r
 113 #define portFPCCR_LSPEN_POS                                     ( 30UL )\r
 114 #define portFPCCR_LSPEN_MASK                            ( 1UL << portFPCCR_LSPEN_POS )\r
 115 /*-----------------------------------------------------------*/\r
 116 \r
 117 /**\r
 118  * @brief Constants required to manipulate the MPU.\r
 119  */\r
 120 #define portMPU_TYPE_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
 121 #define portMPU_CTRL_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 122 #define portMPU_RNR_REG                                         ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
 123 \r
 124 #define portMPU_RBAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
 125 #define portMPU_RLAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
 126 \r
 127 #define portMPU_RBAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
 128 #define portMPU_RLAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
 129 \r
 130 #define portMPU_RBAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
 131 #define portMPU_RLAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
 132 \r
 133 #define portMPU_RBAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
 134 #define portMPU_RLAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
 135 \r
 136 #define portMPU_MAIR0_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
 137 #define portMPU_MAIR1_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
 138 \r
 139 #define portMPU_RBAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 140 #define portMPU_RLAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 141 \r
 142 #define portMPU_MAIR_ATTR0_POS                          ( 0UL )\r
 143 #define portMPU_MAIR_ATTR0_MASK                         ( 0x000000ff )\r
 144 \r
 145 #define portMPU_MAIR_ATTR1_POS                          ( 8UL )\r
 146 #define portMPU_MAIR_ATTR1_MASK                         ( 0x0000ff00 )\r
 147 \r
 148 #define portMPU_MAIR_ATTR2_POS                          ( 16UL )\r
 149 #define portMPU_MAIR_ATTR2_MASK                         ( 0x00ff0000 )\r
 150 \r
 151 #define portMPU_MAIR_ATTR3_POS                          ( 24UL )\r
 152 #define portMPU_MAIR_ATTR3_MASK                         ( 0xff000000 )\r
 153 \r
 154 #define portMPU_MAIR_ATTR4_POS                          ( 0UL )\r
 155 #define portMPU_MAIR_ATTR4_MASK                         ( 0x000000ff )\r
 156 \r
 157 #define portMPU_MAIR_ATTR5_POS                          ( 8UL )\r
 158 #define portMPU_MAIR_ATTR5_MASK                         ( 0x0000ff00 )\r
 159 \r
 160 #define portMPU_MAIR_ATTR6_POS                          ( 16UL )\r
 161 #define portMPU_MAIR_ATTR6_MASK                         ( 0x00ff0000 )\r
 162 \r
 163 #define portMPU_MAIR_ATTR7_POS                          ( 24UL )\r
 164 #define portMPU_MAIR_ATTR7_MASK                         ( 0xff000000 )\r
 165 \r
 166 #define portMPU_RLAR_ATTR_INDEX0                        ( 0UL << 1UL )\r
 167 #define portMPU_RLAR_ATTR_INDEX1                        ( 1UL << 1UL )\r
 168 #define portMPU_RLAR_ATTR_INDEX2                        ( 2UL << 1UL )\r
 169 #define portMPU_RLAR_ATTR_INDEX3                        ( 3UL << 1UL )\r
 170 #define portMPU_RLAR_ATTR_INDEX4                        ( 4UL << 1UL )\r
 171 #define portMPU_RLAR_ATTR_INDEX5                        ( 5UL << 1UL )\r
 172 #define portMPU_RLAR_ATTR_INDEX6                        ( 6UL << 1UL )\r
 173 #define portMPU_RLAR_ATTR_INDEX7                        ( 7UL << 1UL )\r
 174 \r
 175 #define portMPU_RLAR_REGION_ENABLE                      ( 1UL )\r
 176 \r
 177 /* Enable privileged access to unmapped region. */\r
 178 #define portMPU_PRIV_BACKGROUND_ENABLE_BIT      ( 1UL << 2UL )\r
 179 \r
 180 /* Enable MPU. */\r
 181 #define portMPU_ENABLE_BIT                                      ( 1UL << 0UL )\r
 182 \r
 183 /* Expected value of the portMPU_TYPE register. */\r
 184 #define portEXPECTED_MPU_TYPE_VALUE                     ( 8UL << 8UL ) /* 8 regions, unified. */\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 /**\r
 188  * @brief The maximum 24-bit number.\r
 189  *\r
 190  * It is needed because the systick is a 24-bit counter.\r
 191  */\r
 192 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 193 \r
 194 /**\r
 195  * @brief A fiddle factor to estimate the number of SysTick counts that would\r
 196  * have occurred while the SysTick counter is stopped during tickless idle\r
 197  * calculations.\r
 198  */\r
 199 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 200 /*-----------------------------------------------------------*/\r
 201 \r
 202 /**\r
 203  * @brief Constants required to set up the initial stack.\r
 204  */\r
 205 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 206 \r
 207 #if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
 208         /**\r
 209          * @brief Initial EXC_RETURN value.\r
 210          *\r
 211          *     FF         FF         FF         FD\r
 212          * 1111 1111  1111 1111  1111 1111  1111 1101\r
 213          *\r
 214          * Bit[6] - 1 --> The exception was taken from the Secure state.\r
 215          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 216          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 217          * Bit[3] - 1 --> Return to the Thread mode.\r
 218          * Bit[2] - 1 --> Restore registers from the process stack.\r
 219          * Bit[1] - 0 --> Reserved, 0.\r
 220          * Bit[0] - 1 --> The exception was taken to the Secure state.\r
 221          */\r
 222         #define portINITIAL_EXC_RETURN                  ( 0xfffffffd )\r
 223 #else\r
 224         /**\r
 225          * @brief Initial EXC_RETURN value.\r
 226          *\r
 227          *     FF         FF         FF         BC\r
 228          * 1111 1111  1111 1111  1111 1111  1011 1100\r
 229          *\r
 230          * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
 231          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 232          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 233          * Bit[3] - 1 --> Return to the Thread mode.\r
 234          * Bit[2] - 1 --> Restore registers from the process stack.\r
 235          * Bit[1] - 0 --> Reserved, 0.\r
 236          * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
 237          */\r
 238         #define portINITIAL_EXC_RETURN                  ( 0xffffffbc )\r
 239 #endif /* configRUN_FREERTOS_SECURE_ONLY */\r
 240 \r
 241 /**\r
 242  * @brief CONTROL register privileged bit mask.\r
 243  *\r
 244  * Bit[0] in CONTROL register tells the privilege:\r
 245  *  Bit[0] = 0 ==> The task is privileged.\r
 246  *  Bit[0] = 1 ==> The task is not privileged.\r
 247  */\r
 248 #define portCONTROL_PRIVILEGED_MASK                     ( 1UL << 0UL )\r
 249 \r
 250 /**\r
 251  * @brief Initial CONTROL register values.\r
 252  */\r
 253 #define portINITIAL_CONTROL_UNPRIVILEGED        ( 0x3 )\r
 254 #define portINITIAL_CONTROL_PRIVILEGED          ( 0x2 )\r
 255 \r
 256 /**\r
 257  * @brief Let the user override the pre-loading of the initial LR with the\r
 258  * address of prvTaskExitError() in case it messes up unwinding of the stack\r
 259  * in the debugger.\r
 260  */\r
 261 #ifdef configTASK_RETURN_ADDRESS\r
 262         #define portTASK_RETURN_ADDRESS                 configTASK_RETURN_ADDRESS\r
 263 #else\r
 264         #define portTASK_RETURN_ADDRESS                 prvTaskExitError\r
 265 #endif\r
 266 \r
 267 /**\r
 268  * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
 269  * when a task is created. This helps in debugging at the cost of code size.\r
 270  */\r
 271 #define portPRELOAD_REGISTERS                           1\r
 272 \r
 273 /**\r
 274  * @brief A task is created without a secure context, and must call\r
 275  * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
 276  * any secure calls.\r
 277  */\r
 278 #define portNO_SECURE_CONTEXT                           0\r
 279 /*-----------------------------------------------------------*/\r
 280 \r
 281 /**\r
 282  * @brief Used to catch tasks that attempt to return from their implementing\r
 283  * function.\r
 284  */\r
 285 static void prvTaskExitError( void );\r
 286 \r
 287 #if( configENABLE_MPU == 1 )\r
 288         /**\r
 289          * @brief Setup the Memory Protection Unit (MPU).\r
 290          */\r
 291         static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 292 #endif /* configENABLE_MPU */\r
 293 \r
 294 #if( configENABLE_FPU == 1 )\r
 295         /**\r
 296          * @brief Setup the Floating Point Unit (FPU).\r
 297          */\r
 298         static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
 299 #endif /* configENABLE_FPU */\r
 300 \r
 301 /**\r
 302  * @brief Setup the timer to generate the tick interrupts.\r
 303  *\r
 304  * The implementation in this file is weak to allow application writers to\r
 305  * change the timer used to generate the tick interrupt.\r
 306  */\r
 307 void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 308 \r
 309 /**\r
 310  * @brief Checks whether the current execution context is interrupt.\r
 311  *\r
 312  * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
 313  * otherwise.\r
 314  */\r
 315 BaseType_t xPortIsInsideInterrupt( void );\r
 316 \r
 317 /**\r
 318  * @brief Yield the processor.\r
 319  */\r
 320 void vPortYield( void ) PRIVILEGED_FUNCTION;\r
 321 \r
 322 /**\r
 323  * @brief Enter critical section.\r
 324  */\r
 325 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
 326 \r
 327 /**\r
 328  * @brief Exit from critical section.\r
 329  */\r
 330 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
 331 \r
 332 /**\r
 333  * @brief SysTick handler.\r
 334  */\r
 335 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
 336 \r
 337 /**\r
 338  * @brief C part of SVC handler.\r
 339  */\r
 340 portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
 341 /*-----------------------------------------------------------*/\r
 342 \r
 343 /**\r
 344  * @brief Each task maintains its own interrupt status in the critical nesting\r
 345  * variable.\r
 346  */\r
 347 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
 348 \r
 349 #if( configENABLE_TRUSTZONE == 1 )\r
 350         /**\r
 351          * @brief Saved as part of the task context to indicate which context the\r
 352          * task is using on the secure side.\r
 353          */\r
 354         portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
 355 #endif /* configENABLE_TRUSTZONE */\r
 356 \r
 357 #if( configUSE_TICKLESS_IDLE == 1 )\r
 358         /**\r
 359          * @brief The number of SysTick increments that make up one tick period.\r
 360          */\r
 361         static uint32_t ulTimerCountsForOneTick = 0;\r
 362 \r
 363         /**\r
 364          * @brief The maximum number of tick periods that can be suppressed is\r
 365          * limited by the 24 bit resolution of the SysTick timer.\r
 366          */\r
 367         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 368 \r
 369         /**\r
 370          * @brief Compensate for the CPU cycles that pass while the SysTick is\r
 371          * stopped (low power functionality only).\r
 372          */\r
 373         static uint32_t ulStoppedTimerCompensation = 0;\r
 374 #endif /* configUSE_TICKLESS_IDLE */\r
 375 /*-----------------------------------------------------------*/\r
 376 \r
 377 #if( configUSE_TICKLESS_IDLE == 1 )\r
 378         __attribute__(( weak )) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 379         {\r
 380         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 381         TickType_t xModifiableIdleTime;\r
 382 \r
 383                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 384                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 385                 {\r
 386                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 387                 }\r
 388 \r
 389                 /* Stop the SysTick momentarily. The time the SysTick is stopped for is\r
 390                  * accounted for as best it can be, but using the tickless mode will\r
 391                  * inevitably result in some tiny drift of the time maintained by the\r
 392                  * kernel with respect to calendar time. */\r
 393                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 394 \r
 395                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 396                  * tick periods. -1 is used because this code will execute part way\r
 397                  * through one of the tick periods. */\r
 398                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 399                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 400                 {\r
 401                         ulReloadValue -= ulStoppedTimerCompensation;\r
 402                 }\r
 403 \r
 404                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 405                  * method as that will mask interrupts that should exit sleep mode. */\r
 406                 __asm volatile( "cpsid i" ::: "memory" );\r
 407                 __asm volatile( "dsb" );\r
 408                 __asm volatile( "isb" );\r
 409 \r
 410                 /* If a context switch is pending or a task is waiting for the scheduler\r
 411                  * to be un-suspended then abandon the low power entry. */\r
 412                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 413                 {\r
 414                         /* Restart from whatever is left in the count register to complete\r
 415                          * this tick period. */\r
 416                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 417 \r
 418                         /* Restart SysTick. */\r
 419                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 420 \r
 421                         /* Reset the reload register to the value required for normal tick\r
 422                          * periods. */\r
 423                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 424 \r
 425                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 426                          * above. */\r
 427                         __asm volatile( "cpsie i" ::: "memory" );\r
 428                 }\r
 429                 else\r
 430                 {\r
 431                         /* Set the new reload value. */\r
 432                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 433 \r
 434                         /* Clear the SysTick count flag and set the count value back to\r
 435                          * zero. */\r
 436                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 437 \r
 438                         /* Restart SysTick. */\r
 439                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 440 \r
 441                         /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can\r
 442                          * set its parameter to 0 to indicate that its implementation\r
 443                          * contains its own wait for interrupt or wait for event\r
 444                          * instruction, and so wfi should not be executed again. However,\r
 445                          * the original expected idle time variable must remain unmodified,\r
 446                          * so a copy is taken. */\r
 447                         xModifiableIdleTime = xExpectedIdleTime;\r
 448                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 449                         if( xModifiableIdleTime > 0 )\r
 450                         {\r
 451                                 __asm volatile( "dsb" ::: "memory" );\r
 452                                 __asm volatile( "wfi" );\r
 453                                 __asm volatile( "isb" );\r
 454                         }\r
 455                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 456 \r
 457                         /* Re-enable interrupts to allow the interrupt that brought the MCU\r
 458                          * out of sleep mode to execute immediately. See comments above\r
 459                          * the cpsid instruction above. */\r
 460                         __asm volatile( "cpsie i" ::: "memory" );\r
 461                         __asm volatile( "dsb" );\r
 462                         __asm volatile( "isb" );\r
 463 \r
 464                         /* Disable interrupts again because the clock is about to be stopped\r
 465                          * and interrupts that execute while the clock is stopped will\r
 466                          * increase any slippage between the time maintained by the RTOS and\r
 467                          * calendar time. */\r
 468                         __asm volatile( "cpsid i" ::: "memory" );\r
 469                         __asm volatile( "dsb" );\r
 470                         __asm volatile( "isb" );\r
 471 \r
 472                         /* Disable the SysTick clock without reading the\r
 473                          * portNVIC_SYSTICK_CTRL_REG register to ensure the\r
 474                          * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.\r
 475                          * Again, the time the SysTick is stopped for is accounted for as\r
 476                          * best it can be, but using the tickless mode will inevitably\r
 477                          * result in some tiny drift of the time maintained by the kernel\r
 478                          * with respect to calendar time*/\r
 479                         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
 480 \r
 481                         /* Determine if the SysTick clock has already counted to zero and\r
 482                          * been set back to the current reload value (the reload back being\r
 483                          * correct for the entire expected idle time) or if the SysTick is\r
 484                          * yet to count to zero (in which case an interrupt other than the\r
 485                          * SysTick must have brought the system out of sleep mode). */\r
 486                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 487                         {\r
 488                                 uint32_t ulCalculatedLoadValue;\r
 489 \r
 490                                 /* The tick interrupt is already pending, and the SysTick count\r
 491                                  * reloaded with ulReloadValue.  Reset the\r
 492                                  * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 493                                  * period. */\r
 494                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 495 \r
 496                                 /* Don't allow a tiny value, or values that have somehow\r
 497                                  * underflowed because the post sleep hook did something\r
 498                                  * that took too long. */\r
 499                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 500                                 {\r
 501                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 502                                 }\r
 503 \r
 504                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 505 \r
 506                                 /* As the pending tick will be processed as soon as this\r
 507                                  * function exits, the tick value maintained by the tick is\r
 508                                  * stepped forward by one less than the time spent waiting. */\r
 509                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 510                         }\r
 511                         else\r
 512                         {\r
 513                                 /* Something other than the tick interrupt ended the sleep.\r
 514                                  * Work out how long the sleep lasted rounded to complete tick\r
 515                                  * periods (not the ulReload value which accounted for part\r
 516                                  * ticks). */\r
 517                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 518 \r
 519                                 /* How many complete tick periods passed while the processor\r
 520                                  * was waiting? */\r
 521                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 522 \r
 523                                 /* The reload value is set to whatever fraction of a single tick\r
 524                                  * period remains. */\r
 525                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 526                         }\r
 527 \r
 528                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 529                          * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 530                          * value. */\r
 531                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 532                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 533                         vTaskStepTick( ulCompleteTickPeriods );\r
 534                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 535 \r
 536                         /* Exit with interrupts enabled. */\r
 537                         __asm volatile( "cpsie i" ::: "memory" );\r
 538                 }\r
 539         }\r
 540 #endif /* configUSE_TICKLESS_IDLE */\r
 541 /*-----------------------------------------------------------*/\r
 542 \r
 543 __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
 544 {\r
 545         /* Calculate the constants required to configure the tick interrupt. */\r
 546         #if( configUSE_TICKLESS_IDLE == 1 )\r
 547         {\r
 548                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 549                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 550                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 551         }\r
 552         #endif /* configUSE_TICKLESS_IDLE */\r
 553 \r
 554         /* Stop and reset the SysTick. */\r
 555         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 556         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 557 \r
 558         /* Configure SysTick to interrupt at the requested rate. */\r
 559         portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 560         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 561 }\r
 562 /*-----------------------------------------------------------*/\r
 563 \r
 564 static void prvTaskExitError( void )\r
 565 {\r
 566 volatile uint32_t ulDummy = 0UL;\r
 567 \r
 568         /* A function that implements a task must not exit or attempt to return to\r
 569          * its caller as there is nothing to return to. If a task wants to exit it\r
 570          * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
 571          * to be triggered if configASSERT() is defined, then stop here so\r
 572          * application writers can catch the error. */\r
 573         configASSERT( ulCriticalNesting == ~0UL );\r
 574         portDISABLE_INTERRUPTS();\r
 575 \r
 576         while( ulDummy == 0 )\r
 577         {\r
 578                 /* This file calls prvTaskExitError() after the scheduler has been\r
 579                  * started to remove a compiler warning about the function being\r
 580                  * defined but never called.  ulDummy is used purely to quieten other\r
 581                  * warnings about code appearing after this function is called - making\r
 582                  * ulDummy volatile makes the compiler think the function could return\r
 583                  * and therefore not output an 'unreachable code' warning for code that\r
 584                  * appears after it. */\r
 585         }\r
 586 }\r
 587 /*-----------------------------------------------------------*/\r
 588 \r
 589 #if( configENABLE_MPU == 1 )\r
 590         static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
 591         {\r
 592         #if defined( __ARMCC_VERSION )\r
 593                 /* Declaration when these variable are defined in code instead of being\r
 594                  * exported from linker scripts. */\r
 595                 extern uint32_t * __privileged_functions_start__;\r
 596                 extern uint32_t * __privileged_functions_end__;\r
 597                 extern uint32_t * __syscalls_flash_start__;\r
 598                 extern uint32_t * __syscalls_flash_end__;\r
 599                 extern uint32_t * __unprivileged_flash_start__;\r
 600                 extern uint32_t * __unprivileged_flash_end__;\r
 601                 extern uint32_t * __privileged_sram_start__;\r
 602                 extern uint32_t * __privileged_sram_end__;\r
 603         #else\r
 604                 /* Declaration when these variable are exported from linker scripts. */\r
 605                 extern uint32_t __privileged_functions_start__[];\r
 606                 extern uint32_t __privileged_functions_end__[];\r
 607                 extern uint32_t __syscalls_flash_start__[];\r
 608                 extern uint32_t __syscalls_flash_end__[];\r
 609                 extern uint32_t __unprivileged_flash_start__[];\r
 610                 extern uint32_t __unprivileged_flash_end__[];\r
 611                 extern uint32_t __privileged_sram_start__[];\r
 612                 extern uint32_t __privileged_sram_end__[];\r
 613         #endif /* defined( __ARMCC_VERSION ) */\r
 614 \r
 615                 /* Check that the MPU is present. */\r
 616                 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 617                 {\r
 618                         /* MAIR0 - Index 0. */\r
 619                         portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
 620                         /* MAIR0 - Index 1. */\r
 621                         portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
 622 \r
 623                         /* Setup privileged flash as Read Only so that privileged tasks can\r
 624                          * read it but not modify. */\r
 625                         portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
 626                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 627                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 628                                                                 ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
 629                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 630                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 631                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 632 \r
 633                         /* Setup unprivileged flash as Read Only by both privileged and\r
 634                          * unprivileged tasks. All tasks can read it but no-one can modify. */\r
 635                         portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
 636                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 637                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 638                                                                 ( portMPU_REGION_READ_ONLY );\r
 639                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 640                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 641                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 642 \r
 643                         /* Setup unprivileged syscalls flash as Read Only by both privileged\r
 644                          * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
 645                         portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
 646                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 647                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 648                                                                 ( portMPU_REGION_READ_ONLY );\r
 649                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 650                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 651                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 652 \r
 653                         /* Setup RAM containing kernel data for privileged access only. */\r
 654                         portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
 655                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 656                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 657                                                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 658                                                                 ( portMPU_REGION_EXECUTE_NEVER );\r
 659                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 660                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 661                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 662 \r
 663                         /* Enable mem fault. */\r
 664                         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;\r
 665 \r
 666                         /* Enable MPU with privileged background access i.e. unmapped\r
 667                          * regions have privileged access. */\r
 668                         portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );\r
 669                 }\r
 670         }\r
 671 #endif /* configENABLE_MPU */\r
 672 /*-----------------------------------------------------------*/\r
 673 \r
 674 #if( configENABLE_FPU == 1 )\r
 675         static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
 676         {\r
 677                 #if( configENABLE_TRUSTZONE == 1 )\r
 678                 {\r
 679                         /* Enable non-secure access to the FPU. */\r
 680                         SecureInit_EnableNSFPUAccess();\r
 681                 }\r
 682                 #endif /* configENABLE_TRUSTZONE */\r
 683 \r
 684                 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
 685                  * unprivileged code should be able to access FPU. CP11 should be\r
 686                  * programmed to the same value as CP10. */\r
 687                 *( portCPACR ) |=       (       ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
 688                                                                 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
 689                                                         );\r
 690 \r
 691                 /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
 692                  * context on exception entry and restore on exception return.\r
 693                  * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
 694                 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
 695         }\r
 696 #endif /* configENABLE_FPU */\r
 697 /*-----------------------------------------------------------*/\r
 698 \r
 699 void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
 700 {\r
 701         /* Set a PendSV to request a context switch. */\r
 702         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 703 \r
 704         /* Barriers are normally not required but do ensure the code is\r
 705          * completely within the specified behaviour for the architecture. */\r
 706         __asm volatile( "dsb" ::: "memory" );\r
 707         __asm volatile( "isb" );\r
 708 }\r
 709 /*-----------------------------------------------------------*/\r
 710 \r
 711 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
 712 {\r
 713         portDISABLE_INTERRUPTS();\r
 714         ulCriticalNesting++;\r
 715 \r
 716         /* Barriers are normally not required but do ensure the code is\r
 717          * completely within the specified behaviour for the architecture. */\r
 718         __asm volatile( "dsb" ::: "memory" );\r
 719         __asm volatile( "isb" );\r
 720 }\r
 721 /*-----------------------------------------------------------*/\r
 722 \r
 723 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
 724 {\r
 725         configASSERT( ulCriticalNesting );\r
 726         ulCriticalNesting--;\r
 727 \r
 728         if( ulCriticalNesting == 0 )\r
 729         {\r
 730                 portENABLE_INTERRUPTS();\r
 731         }\r
 732 }\r
 733 /*-----------------------------------------------------------*/\r
 734 \r
 735 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
 736 {\r
 737 uint32_t ulPreviousMask;\r
 738 \r
 739         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
 740         {\r
 741                 /* Increment the RTOS tick. */\r
 742                 if( xTaskIncrementTick() != pdFALSE )\r
 743                 {\r
 744                         /* Pend a context switch. */\r
 745                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 746                 }\r
 747         }\r
 748         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
 749 }\r
 750 /*-----------------------------------------------------------*/\r
 751 \r
 752 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
 753 {\r
 754 #if( configENABLE_MPU == 1 )\r
 755         #if defined( __ARMCC_VERSION )\r
 756                 /* Declaration when these variable are defined in code instead of being\r
 757                  * exported from linker scripts. */\r
 758                 extern uint32_t * __syscalls_flash_start__;\r
 759                 extern uint32_t * __syscalls_flash_end__;\r
 760         #else\r
 761                 /* Declaration when these variable are exported from linker scripts. */\r
 762                 extern uint32_t __syscalls_flash_start__[];\r
 763                 extern uint32_t __syscalls_flash_end__[];\r
 764         #endif /* defined( __ARMCC_VERSION ) */\r
 765 #endif /* configENABLE_MPU */\r
 766 \r
 767 uint32_t ulPC;\r
 768 \r
 769 #if( configENABLE_TRUSTZONE == 1 )\r
 770         uint32_t ulR0;\r
 771         #if( configENABLE_MPU == 1 )\r
 772                 uint32_t ulControl, ulIsTaskPrivileged;\r
 773         #endif /* configENABLE_MPU */\r
 774 #endif /* configENABLE_TRUSTZONE */\r
 775 uint8_t ucSVCNumber;\r
 776 \r
 777         /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
 778          * R12, LR, PC, xPSR. */\r
 779         ulPC = pulCallerStackAddress[ 6 ];\r
 780         ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
 781 \r
 782         switch( ucSVCNumber )\r
 783         {\r
 784                 #if( configENABLE_TRUSTZONE == 1 )\r
 785                         case portSVC_ALLOCATE_SECURE_CONTEXT:\r
 786                         {\r
 787                                 /* R0 contains the stack size passed as parameter to the\r
 788                                  * vPortAllocateSecureContext function. */\r
 789                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 790 \r
 791                                 #if( configENABLE_MPU == 1 )\r
 792                                 {\r
 793                                         /* Read the CONTROL register value. */\r
 794                                         __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );\r
 795 \r
 796                                         /* The task that raised the SVC is privileged if Bit[0]\r
 797                                          * in the CONTROL register is 0. */\r
 798                                         ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
 799 \r
 800                                         /* Allocate and load a context for the secure task. */\r
 801                                         xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
 802                                 }\r
 803                                 #else\r
 804                                 {\r
 805                                         /* Allocate and load a context for the secure task. */\r
 806                                         xSecureContext = SecureContext_AllocateContext( ulR0 );\r
 807                                 }\r
 808                                 #endif /* configENABLE_MPU */\r
 809 \r
 810                                 configASSERT( xSecureContext != NULL );\r
 811                                 SecureContext_LoadContext( xSecureContext );\r
 812                         }\r
 813                         break;\r
 814 \r
 815                         case portSVC_FREE_SECURE_CONTEXT:\r
 816                         {\r
 817                                 /* R0 contains the secure context handle to be freed. */\r
 818                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 819 \r
 820                                 /* Free the secure context. */\r
 821                                 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
 822                         }\r
 823                         break;\r
 824                 #endif /* configENABLE_TRUSTZONE */\r
 825 \r
 826                 case portSVC_START_SCHEDULER:\r
 827                 {\r
 828                         #if( configENABLE_TRUSTZONE == 1 )\r
 829                         {\r
 830                                 /* De-prioritize the non-secure exceptions so that the\r
 831                                  * non-secure pendSV runs at the lowest priority. */\r
 832                                 SecureInit_DePrioritizeNSExceptions();\r
 833 \r
 834                                 /* Initialize the secure context management system. */\r
 835                                 SecureContext_Init();\r
 836                         }\r
 837                         #endif /* configENABLE_TRUSTZONE */\r
 838 \r
 839                         #if( configENABLE_FPU == 1 )\r
 840                         {\r
 841                                 /* Setup the Floating Point Unit (FPU). */\r
 842                                 prvSetupFPU();\r
 843                         }\r
 844                         #endif /* configENABLE_FPU */\r
 845 \r
 846                         /* Setup the context of the first task so that the first task starts\r
 847                          * executing. */\r
 848                         vRestoreContextOfFirstTask();\r
 849                 }\r
 850                 break;\r
 851 \r
 852                 #if( configENABLE_MPU == 1 )\r
 853                         case portSVC_RAISE_PRIVILEGE:\r
 854                         {\r
 855                                 /* Only raise the privilege, if the svc was raised from any of\r
 856                                  * the system calls. */\r
 857                                 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
 858                                         ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
 859                                 {\r
 860                                         vRaisePrivilege();\r
 861                                 }\r
 862                         }\r
 863                         break;\r
 864                 #endif /* configENABLE_MPU */\r
 865 \r
 866                 default:\r
 867                 {\r
 868                         /* Incorrect SVC call. */\r
 869                         configASSERT( pdFALSE );\r
 870                 }\r
 871         }\r
 872 }\r
 873 /*-----------------------------------------------------------*/\r
 874 \r
 875 #if( configENABLE_MPU == 1 )\r
 876         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
 877 #else\r
 878         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
 879 #endif /* configENABLE_MPU */\r
 880 {\r
 881         /* Simulate the stack frame as it would be created by a context switch\r
 882          * interrupt. */\r
 883         #if( portPRELOAD_REGISTERS == 0 )\r
 884         {\r
 885                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 886                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 887                 pxTopOfStack--;\r
 888                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 889                 pxTopOfStack--;\r
 890                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 891                 pxTopOfStack -= 5;                                                                                      /* R12, R3, R2 and R1. */\r
 892                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 893                 pxTopOfStack -= 9;                                                                                      /* R11..R4, EXC_RETURN. */\r
 894                 *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 895 \r
 896                 #if( configENABLE_MPU == 1 )\r
 897                 {\r
 898                         pxTopOfStack--;\r
 899                         if( xRunPrivileged == pdTRUE )\r
 900                         {\r
 901                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 902                         }\r
 903                         else\r
 904                         {\r
 905                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 906                         }\r
 907                 }\r
 908                 #endif /* configENABLE_MPU */\r
 909 \r
 910                 pxTopOfStack--;\r
 911                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 912 \r
 913                 #if( configENABLE_TRUSTZONE == 1 )\r
 914                 {\r
 915                         pxTopOfStack--;\r
 916                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 917                 }\r
 918                 #endif /* configENABLE_TRUSTZONE */\r
 919         }\r
 920         #else /* portPRELOAD_REGISTERS */\r
 921         {\r
 922                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 923                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 924                 pxTopOfStack--;\r
 925                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 926                 pxTopOfStack--;\r
 927                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 928                 pxTopOfStack--;\r
 929                 *pxTopOfStack = ( StackType_t ) 0x12121212UL;                           /* R12 */\r
 930                 pxTopOfStack--;\r
 931                 *pxTopOfStack = ( StackType_t ) 0x03030303UL;                           /* R3 */\r
 932                 pxTopOfStack--;\r
 933                 *pxTopOfStack = ( StackType_t ) 0x02020202UL;                           /* R2 */\r
 934                 pxTopOfStack--;\r
 935                 *pxTopOfStack = ( StackType_t ) 0x01010101UL;                           /* R1 */\r
 936                 pxTopOfStack--;\r
 937                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 938                 pxTopOfStack--;\r
 939                 *pxTopOfStack = ( StackType_t ) 0x11111111UL;                           /* R11 */\r
 940                 pxTopOfStack--;\r
 941                 *pxTopOfStack = ( StackType_t ) 0x10101010UL;                           /* R10 */\r
 942                 pxTopOfStack--;\r
 943                 *pxTopOfStack = ( StackType_t ) 0x09090909UL;                           /* R09 */\r
 944                 pxTopOfStack--;\r
 945                 *pxTopOfStack = ( StackType_t ) 0x08080808UL;                           /* R08 */\r
 946                 pxTopOfStack--;\r
 947                 *pxTopOfStack = ( StackType_t ) 0x07070707UL;                           /* R07 */\r
 948                 pxTopOfStack--;\r
 949                 *pxTopOfStack = ( StackType_t ) 0x06060606UL;                           /* R06 */\r
 950                 pxTopOfStack--;\r
 951                 *pxTopOfStack = ( StackType_t ) 0x05050505UL;                           /* R05 */\r
 952                 pxTopOfStack--;\r
 953                 *pxTopOfStack = ( StackType_t ) 0x04040404UL;                           /* R04 */\r
 954                 pxTopOfStack--;\r
 955                 *pxTopOfStack = portINITIAL_EXC_RETURN;                                         /* EXC_RETURN */\r
 956 \r
 957                 #if( configENABLE_MPU == 1 )\r
 958                 {\r
 959                         pxTopOfStack--;\r
 960                         if( xRunPrivileged == pdTRUE )\r
 961                         {\r
 962                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 963                         }\r
 964                         else\r
 965                         {\r
 966                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 967                         }\r
 968                 }\r
 969                 #endif /* configENABLE_MPU */\r
 970 \r
 971                 pxTopOfStack--;\r
 972                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 973 \r
 974                 #if( configENABLE_TRUSTZONE == 1 )\r
 975                 {\r
 976                         pxTopOfStack--;\r
 977                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 978                 }\r
 979                 #endif /* configENABLE_TRUSTZONE */\r
 980         }\r
 981         #endif /* portPRELOAD_REGISTERS */\r
 982 \r
 983         return pxTopOfStack;\r
 984 }\r
 985 /*-----------------------------------------------------------*/\r
 986 \r
 987 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
 988 {\r
 989         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
 990         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 991         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 992 \r
 993         #if( configENABLE_MPU == 1 )\r
 994         {\r
 995                 /* Setup the Memory Protection Unit (MPU). */\r
 996                 prvSetupMPU();\r
 997         }\r
 998         #endif /* configENABLE_MPU */\r
 999 \r
1000         /* Start the timer that generates the tick ISR. Interrupts are disabled\r
1001          * here already. */\r
1002         vPortSetupTimerInterrupt();\r
1003 \r
1004         /* Initialize the critical nesting count ready for the first task. */\r
1005         ulCriticalNesting = 0;\r
1006 \r
1007         /* Start the first task. */\r
1008         vStartFirstTask();\r
1009 \r
1010         /* Should never get here as the tasks will now be executing. Call the task\r
1011          * exit error function to prevent compiler warnings about a static function\r
1012          * not being called in the case that the application writer overrides this\r
1013          * functionality by defining configTASK_RETURN_ADDRESS. Call\r
1014          * vTaskSwitchContext() so link time optimization does not remove the\r
1015          * symbol. */\r
1016         vTaskSwitchContext();\r
1017         prvTaskExitError();\r
1018 \r
1019         /* Should not get here. */\r
1020         return 0;\r
1021 }\r
1022 /*-----------------------------------------------------------*/\r
1023 \r
1024 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
1025 {\r
1026         /* Not implemented in ports where there is nothing to return to.\r
1027          * Artificially force an assert. */\r
1028         configASSERT( ulCriticalNesting == 1000UL );\r
1029 }\r
1030 /*-----------------------------------------------------------*/\r
1031 \r
1032 #if( configENABLE_MPU == 1 )\r
1033         void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
1034         {\r
1035         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
1036         int32_t lIndex = 0;\r
1037 \r
1038                 /* Setup MAIR0. */\r
1039                 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
1040                 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
1041 \r
1042                 /* This function is called automatically when the task is created - in\r
1043                  * which case the stack region parameters will be valid.  At all other\r
1044                  * times the stack parameters will not be valid and it is assumed that\r
1045                  * the stack region has already been configured. */\r
1046                 if( ulStackDepth > 0 )\r
1047                 {\r
1048                         /* Define the region that allows access to the stack. */\r
1049                         ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
1050                         ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
1051                         ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
1052 \r
1053                         xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |\r
1054                                                                                                                         ( portMPU_REGION_NON_SHAREABLE ) |\r
1055                                                                                                                         ( portMPU_REGION_READ_WRITE ) |\r
1056                                                                                                                         ( portMPU_REGION_EXECUTE_NEVER );\r
1057 \r
1058                         xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |\r
1059                                                                                                                         ( portMPU_RLAR_ATTR_INDEX0 ) |\r
1060                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
1061                 }\r
1062 \r
1063                 /* User supplied configurable regions. */\r
1064                 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
1065                 {\r
1066                         /* If xRegions is NULL i.e. the task has not specified any MPU\r
1067                          * region, the else part ensures that all the configurable MPU\r
1068                          * regions are invalidated. */\r
1069                         if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
1070                         {\r
1071                                 /* Translate the generic region definition contained in xRegions\r
1072                                  * into the ARMv8 specific MPU settings that are then stored in\r
1073                                  * xMPUSettings. */\r
1074                                 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
1075                                 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
1076                                 ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
1077 \r
1078                                 /* Start address. */\r
1079                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =       ( ulRegionStartAddress ) |\r
1080                                                                                                                                                         ( portMPU_REGION_NON_SHAREABLE );\r
1081 \r
1082                                 /* RO/RW. */\r
1083                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
1084                                 {\r
1085                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
1086                                 }\r
1087                                 else\r
1088                                 {\r
1089                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
1090                                 }\r
1091 \r
1092                                 /* XN. */\r
1093                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
1094                                 {\r
1095                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
1096                                 }\r
1097 \r
1098                                 /* End Address. */\r
1099                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =       ( ulRegionEndAddress ) |\r
1100                                                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
1101 \r
1102                                 /* Normal memory/ Device memory. */\r
1103                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
1104                                 {\r
1105                                         /* Attr1 in MAIR0 is configured as device memory. */\r
1106                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
1107                                 }\r
1108                                 else\r
1109                                 {\r
1110                                         /* Attr1 in MAIR0 is configured as normal memory. */\r
1111                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
1112                                 }\r
1113                         }\r
1114                         else\r
1115                         {\r
1116                                 /* Invalidate the region. */\r
1117                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
1118                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
1119                         }\r
1120 \r
1121                         lIndex++;\r
1122                 }\r
1123         }\r
1124 #endif /* configENABLE_MPU */\r
1125 /*-----------------------------------------------------------*/\r
1126 \r
1127 BaseType_t xPortIsInsideInterrupt( void )\r
1128 {\r
1129 uint32_t ulCurrentInterrupt;\r
1130 BaseType_t xReturn;\r
1131 \r
1132         /* Obtain the number of the currently executing interrupt. Interrupt Program\r
1133          * Status Register (IPSR) holds the exception number of the currently-executing\r
1134          * exception or zero for Thread mode.*/\r
1135         __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
1136 \r
1137         if( ulCurrentInterrupt == 0 )\r
1138         {\r
1139                 xReturn = pdFALSE;\r
1140         }\r
1141         else\r
1142         {\r
1143                 xReturn = pdTRUE;\r
1144         }\r
1145 \r
1146         return xReturn;\r
1147 }\r
1148 /*-----------------------------------------------------------*/