1 /* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
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3 /*This file has been prepared for Doxygen automatic documentation generation.*/
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4 /*! \file *********************************************************************
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6 * \brief PHY abstraction layer for AVR32 UC3 on EVK1100.
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8 * - Compiler: GNU GCC for AVR32
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9 * - Supported devices: All AVR32 devices can be used.
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12 * \author Atmel Corporation: http://www.atmel.com \n
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13 * Support email: avr32@atmel.com
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15 *****************************************************************************/
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17 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
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19 * Redistribution and use in source and binary forms, with or without
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20 * modification, are permitted provided that the following conditions are met:
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22 * 1. Redistributions of source code must retain the above copyright notice,
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23 * this list of conditions and the following disclaimer.
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25 * 2. Redistributions in binary form must reproduce the above copyright notice,
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26 * this list of conditions and the following disclaimer in the documentation
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27 * and/or other materials provided with the distribution.
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29 * 3. The name of ATMEL may not be used to endorse or promote products derived
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30 * from this software without specific prior written permission.
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32 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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33 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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34 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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35 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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36 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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44 /* DP83848 registers. */
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45 /*! Generic MII registers. */
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46 #define PHY_BMCR 0x00 /* Basic mode control register */
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47 #define PHY_BMSR 0x01 /* Basic mode status register */
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48 #define PHY_PHYSID1 0x02 /* PHYS ID 1 */
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49 #define PHY_PHYSID2 0x03 /* PHYS ID 2 */
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50 #define PHY_ADVERTISE 0x04 /* Advertisement control reg */
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51 #define PHY_LPA 0x05 /* Link partner ability reg */
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53 #if BOARD == EVK1100
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54 /*! Extended registers for DP83848 */
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55 #define PHY_RBR 0x17 /* RMII Bypass reg */
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56 #define PHY_MICR 0x11 /* Interrupt Control reg */
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57 #define PHY_MISR 0x12 /* Interrupt Status reg */
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58 #define PHY_PHYCR 0x19 /* Phy CTRL reg */
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62 /*! Basic mode control register. */
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63 #define BMCR_RESV 0x007f /* Unused... */
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64 #define BMCR_CTST 0x0080 /* Collision test */
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65 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
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66 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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67 #define BMCR_ISOLATE 0x0400 /* Disconnect PHY from MII */
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68 #define BMCR_PDOWN 0x0800 /* Powerdown the PHY */
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69 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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70 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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71 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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72 #define BMCR_RESET 0x8000 /* Reset the PHY */
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74 /*! Basic mode status register. */
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75 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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76 #define BMSR_JCD 0x0002 /* Jabber detected */
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77 #define BMSR_LSTATUS 0x0004 /* Link status */
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78 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
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79 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
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80 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
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81 #define BMSR_RESV 0x00c0 /* Unused... */
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82 #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
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83 #define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */
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84 #define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */
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85 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
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86 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
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87 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
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88 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
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89 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
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91 /*! Advertisement control register. */
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92 #define ADVERTISE_SLCT 0x001f /* Selector bits */
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93 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
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94 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
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95 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
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96 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
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97 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
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98 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
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99 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
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100 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
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101 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
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102 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
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103 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
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104 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
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105 #define ADVERTISE_RESV 0x1000 /* Unused... */
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106 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
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107 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
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108 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
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110 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
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111 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
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112 ADVERTISE_100HALF | ADVERTISE_100FULL)
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114 /*! Link partner ability register. */
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115 #define LPA_SLCT 0x001f /* Same as advertise selector */
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116 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
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117 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
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118 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
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119 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
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120 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
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121 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
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122 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
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123 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
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124 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
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125 #define LPA_PAUSE_CAP 0x0400 /* Can pause */
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126 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
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127 #define LPA_RESV 0x1000 /* Unused... */
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128 #define LPA_RFAULT 0x2000 /* Link partner faulted */
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129 #define LPA_LPACK 0x4000 /* Link partner acked us */
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130 #define LPA_NPAGE 0x8000 /* Next page bit */
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132 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
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133 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
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135 #if BOARD == EVK1100
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136 /*! RMII Bypass Register */
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137 #define RBR_RMII 0x0020 /* RMII Mode */
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138 /*! Interrupt Ctrl Register */
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139 #define MICR_INTEN 0x0002 /* Enable interrupts */
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140 #define MICR_INTOE 0x0001 /* Enable INT output */
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141 /*! Interrupt Status Register */
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142 #define MISR_ED_INT_EN 0x0040 /* Energy Detect enabled */
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143 #define MISR_LINK_INT_EN 0x0020 /* Link status change enabled */
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144 #define MISR_SPD_INT_EN 0x0010 /* Speed change enabled */
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145 #define MISR_DP_INT_EN 0x0008 /* Duplex mode change enabled */
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146 #define MISR_ANC_INT_EN 0x0004 /* Auto-Neg complete enabled */
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147 #define MISR_FHF_INT_EN 0x0002 /* False Carrier enabled */
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148 #define MISR_RHF_INT_EN 0x0001 /* Receive Error enabled */
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149 #define MISR_ED_INT 0x4000 /* Energy Detect */
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150 #define MISR_LINK_INT 0x2000 /* Link status change */
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151 #define MISR_SPD_INT 0x1000 /* Speed change */
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152 #define MISR_DP_INT 0x0800 /* Duplex mode change */
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153 #define MISR_ANC_INT 0x0400 /* Auto-Neg complete */
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154 #define MISR_FHF_INT 0x0200 /* False Carrier */
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155 #define MISR_RHF_INT 0x0100 /* Receive Error */
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156 /*! Phy Ctrl Register */
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157 #define PHYCR_MDIX_EN 0x8000 /* Enable Auto MDIX */
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158 #define PHYCR_MDIX_FORCE 0x4000 /* Force MDIX crossed */
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162 #define MII_DP83848_ID 0x20005C90 /* 0x00225541 */
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165 #define DP83848_PHY_ADDR 0x01
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