begriffs open source - freertos/blob - portable/GCC/ARM_CM55/non_secure/portasm.c

   1 /*
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   4  * Copyright 2024 Arm Limited and/or its affiliates
   5  * <open-source-office@arm.com>
   6  *
   7  * SPDX-License-Identifier: MIT
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  10  * this software and associated documentation files (the "Software"), to deal in
  11  * the Software without restriction, including without limitation the rights to
  12  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  13  * the Software, and to permit persons to whom the Software is furnished to do so,
  14  * subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in all
  17  * copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  21  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  22  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  23  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  24  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * https://www.FreeRTOS.org
  27  * https://github.com/FreeRTOS
  28  *
  29  */
  30
  31 /* Standard includes. */
  32 #include <stdint.h>
  33
  34 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  35  * is defined correctly and privileged functions are placed in correct sections. */
  36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  37
  38 /* Portasm includes. */
  39 #include "portasm.h"
  40
  41 /* System call numbers includes. */
  42 #include "mpu_syscall_numbers.h"
  43
  44 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  45  * header files. */
  46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  47
  48 #if ( configENABLE_MPU == 1 )
  49
  50     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  51     {
  52         __asm volatile
  53         (
  54             " .syntax unified                                 \n"
  55             "                                                 \n"
  56             " program_mpu_first_task:                         \n"
  57             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  58             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
  59             "                                                 \n"
  60             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
  61             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  62             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  63             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
  64             "    str r2, [r1]                                 \n" /* Disable MPU. */
  65             "                                                 \n"
  66             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
  67             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
  68             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
  69             "    str r1, [r2]                                 \n" /* Program MAIR0. */
  70             "                                                 \n"
  71             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
  72             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
  73             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  74             "                                                 \n"
  75             "    movs r3, #4                                  \n" /* r3 = 4. */
  76             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
  77             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  78             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  79             "                                                 \n"
  80             #if ( configTOTAL_MPU_REGIONS == 16 )
  81                 "    movs r3, #8                                  \n" /* r3 = 8. */
  82                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
  83                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  84                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  85                 "    movs r3, #12                                 \n" /* r3 = 12. */
  86                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
  87                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
  88                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  89             #endif /* configTOTAL_MPU_REGIONS == 16 */
  90             "                                                 \n"
  91             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  92             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  93             "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
  94             "    str r2, [r1]                                 \n" /* Enable MPU. */
  95             "    dsb                                          \n" /* Force memory writes before continuing. */
  96             "                                                 \n"
  97             " restore_context_first_task:                     \n"
  98             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  99             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 100             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 101             "                                                 \n"
 102             " restore_special_regs_first_task:                \n"
 103             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 104             "    msr psp, r3                                  \n"
 105             "    msr psplim, r4                               \n"
 106             "    msr control, r5                              \n"
 107             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 108             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 109             "                                                 \n"
 110             " restore_general_regs_first_task:                \n"
 111             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 112             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 113             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 114             "                                                 \n"
 115             " restore_context_done_first_task:                \n"
 116             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 117             "    mov r0, #0                                   \n"
 118             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
 119             "    bx lr                                        \n"
 120         );
 121     }
 122
 123 #else /* configENABLE_MPU */
 124
 125     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 126     {
 127         __asm volatile
 128         (
 129             "   .syntax unified                                 \n"
 130             "                                                   \n"
 131             "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 132             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
 133             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 134             "                                                   \n"
 135             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
 136             "   ldr  r4, =xSecureContext                        \n"
 137             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
 138             "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
 139             "   mrs  r1, control                                \n" /* Obtain current control register value. */
 140             "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
 141             "   msr control, r1                                 \n" /* Write back the new control register value. */
 142             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
 143             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
 144             "   isb                                             \n"
 145             "   mov  r0, #0                                     \n"
 146             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
 147             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
 148         );
 149     }
 150
 151 #endif /* configENABLE_MPU */
 152 /*-----------------------------------------------------------*/
 153
 154 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 155 {
 156     __asm volatile
 157     (
 158         "   .syntax unified                                 \n"
 159         "                                                   \n"
 160         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 161         "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
 162         "   ite ne                                          \n"
 163         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 164         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 165         "   bx lr                                           \n" /* Return. */
 166         ::: "r0", "memory"
 167     );
 168 }
 169 /*-----------------------------------------------------------*/
 170
 171 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 172 {
 173     __asm volatile
 174     (
 175         "   .syntax unified                                 \n"
 176         "                                                   \n"
 177         "   mrs r0, control                                 \n" /* Read the CONTROL register. */
 178         "   bic r0, #1                                      \n" /* Clear the bit 0. */
 179         "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
 180         "   bx lr                                           \n" /* Return to the caller. */
 181         ::: "r0", "memory"
 182     );
 183 }
 184 /*-----------------------------------------------------------*/
 185
 186 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 187 {
 188     __asm volatile
 189     (
 190         "   .syntax unified                                 \n"
 191         "                                                   \n"
 192         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 193         "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
 194         "   msr control, r0                                 \n" /* CONTROL = r0. */
 195         "   bx lr                                           \n" /* Return to the caller. */
 196         ::: "r0", "memory"
 197     );
 198 }
 199 /*-----------------------------------------------------------*/
 200
 201 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 202 {
 203     __asm volatile
 204     (
 205         "   .syntax unified                                 \n"
 206         "                                                   \n"
 207         "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
 208         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
 209         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
 210         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
 211         "   cpsie i                                         \n" /* Globally enable interrupts. */
 212         "   cpsie f                                         \n"
 213         "   dsb                                             \n"
 214         "   isb                                             \n"
 215         "   svc %0                                          \n" /* System call to start the first task. */
 216         "   nop                                             \n"
 217         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 218     );
 219 }
 220 /*-----------------------------------------------------------*/
 221
 222 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 223 {
 224     __asm volatile
 225     (
 226         "   .syntax unified                                 \n"
 227         "                                                   \n"
 228         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
 229         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 230         "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 231         "   dsb                                             \n"
 232         "   isb                                             \n"
 233         "   bx lr                                           \n" /* Return. */
 234         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 235     );
 236 }
 237 /*-----------------------------------------------------------*/
 238
 239 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 240 {
 241     __asm volatile
 242     (
 243         "   .syntax unified                                 \n"
 244         "                                                   \n"
 245         "   msr basepri, r0                                 \n" /* basepri = ulMask. */
 246         "   dsb                                             \n"
 247         "   isb                                             \n"
 248         "   bx lr                                           \n" /* Return. */
 249         ::: "memory"
 250     );
 251 }
 252 /*-----------------------------------------------------------*/
 253
 254 #if ( configENABLE_MPU == 1 )
 255
 256     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 257     {
 258         __asm volatile
 259         (
 260             " .syntax unified                                 \n"
 261             " .extern SecureContext_SaveContext               \n"
 262             " .extern SecureContext_LoadContext               \n"
 263             "                                                 \n"
 264             " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 265             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 266             " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 267             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 268             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
 269             "                                                 \n"
 270             " cbz r0, save_ns_context                         \n" /* No secure context to save. */
 271             " save_s_context:                                 \n"
 272             "    push {r0-r2, lr}                             \n"
 273             "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 274             "    pop {r0-r2, lr}                              \n"
 275             "                                                 \n"
 276             " save_ns_context:                                \n"
 277             "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
 278             "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 279             "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 280             "                                                 \n"
 281             " save_general_regs:                              \n"
 282             "    mrs r3, psp                                  \n"
 283             "                                                 \n"
 284             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 285                 "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
 286                 "    tst lr, #0x10                                \n"
 287                 "    ittt eq                                      \n"
 288                 "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
 289                 "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
 290                 "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
 291                 "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
 292             #endif /* configENABLE_FPU || configENABLE_MVE */
 293             "                                                 \n"
 294             "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
 295             "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
 296             "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
 297             "                                                 \n"
 298             " save_special_regs:                              \n"
 299             "    mrs r3, psp                                  \n" /* r3 = PSP. */
 300             "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
 301             "    mrs r5, control                              \n" /* r5 = CONTROL. */
 302             "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
 303             "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
 304             "                                                 \n"
 305             " select_next_task:                               \n"
 306             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 307             "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 308             "    dsb                                          \n"
 309             "    isb                                          \n"
 310             "    bl vTaskSwitchContext                        \n"
 311             "    mov r0, #0                                   \n" /* r0 = 0. */
 312             "    msr basepri, r0                              \n" /* Enable interrupts. */
 313             "                                                 \n"
 314             " program_mpu:                                    \n"
 315             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 316             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
 317             "                                                 \n"
 318             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
 319             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 320             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 321             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
 322             "    str r2, [r1]                                 \n" /* Disable MPU. */
 323             "                                                 \n"
 324             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
 325             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
 326             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
 327             "    str r1, [r2]                                 \n" /* Program MAIR0. */
 328             "                                                 \n"
 329             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
 330             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
 331             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 332             "                                                 \n"
 333             "    movs r3, #4                                  \n" /* r3 = 4. */
 334             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
 335             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 336             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 337             "                                                 \n"
 338             #if ( configTOTAL_MPU_REGIONS == 16 )
 339                 "    movs r3, #8                                  \n" /* r3 = 8. */
 340                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
 341                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 342                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 343                 "    movs r3, #12                                 \n" /* r3 = 12. */
 344                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
 345                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 346                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 347             #endif /* configTOTAL_MPU_REGIONS == 16 */
 348             "                                                 \n"
 349             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 350             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
 351             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
 352             "   str r2, [r1]                                  \n" /* Enable MPU. */
 353             "   dsb                                           \n" /* Force memory writes before continuing. */
 354             "                                                 \n"
 355             " restore_context:                                \n"
 356             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 357             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 358             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 359             "                                                 \n"
 360             " restore_special_regs:                           \n"
 361             "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
 362             "    msr psp, r3                                  \n"
 363             "    msr psplim, r4                               \n"
 364             "    msr control, r5                              \n"
 365             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 366             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 367             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
 368             "                                                 \n"
 369             " restore_s_context:                              \n"
 370             "    push {r1-r3, lr}                             \n"
 371             "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 372             "    pop {r1-r3, lr}                              \n"
 373             "                                                 \n"
 374             " restore_ns_context:                             \n"
 375             "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
 376             "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 377             "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 378             "                                                 \n"
 379             " restore_general_regs:                           \n"
 380             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 381             "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 382             "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
 383             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 384                 "    tst lr, #0x10                                \n"
 385                 "    ittt eq                                      \n"
 386                 "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
 387                 "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
 388                 "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
 389             #endif /* configENABLE_FPU || configENABLE_MVE */
 390             "                                                 \n"
 391             " restore_context_done:                           \n"
 392             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 393             "    bx lr                                        \n"
 394             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 395         );
 396     }
 397
 398 #else /* configENABLE_MPU */
 399
 400     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 401     {
 402         __asm volatile
 403         (
 404             "   .syntax unified                                 \n"
 405             "   .extern SecureContext_SaveContext               \n"
 406             "   .extern SecureContext_LoadContext               \n"
 407             "                                                   \n"
 408             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 409             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 410             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 411             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
 412             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
 413             "                                                   \n"
 414             "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
 415             "   push {r0-r2, r14}                               \n"
 416             "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 417             "   pop {r0-r3}                                     \n" /* LR is now in r3. */
 418             "   mov lr, r3                                      \n" /* LR = r3. */
 419             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 420             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 421             "                                                   \n"
 422             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 423             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB.*/
 424             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
 425             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 426             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 427             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 428             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 429             "   b select_next_task                              \n"
 430             "                                                   \n"
 431             " save_ns_context:                                  \n"
 432             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 433             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 434             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 435                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 436                 "   it eq                                       \n"
 437                 "   vstmdbeq r2!, {s16-s31}                     \n" /* Store the additional FP context registers which are not saved automatically. */
 438             #endif /* configENABLE_FPU || configENABLE_MVE */
 439             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
 440             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 441             "   adds r2, r2, #12                                \n" /* r2 = r2 + 12. */
 442             "   stm r2, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
 443             "   mrs r1, psplim                                  \n" /* r1 = PSPLIM. */
 444             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 445             "   subs r2, r2, #12                                \n" /* r2 = r2 - 12. */
 446             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 447             "                                                   \n"
 448             " select_next_task:                                 \n"
 449             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 450             "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 451             "   dsb                                             \n"
 452             "   isb                                             \n"
 453             "   bl vTaskSwitchContext                           \n"
 454             "   mov r0, #0                                      \n" /* r0 = 0. */
 455             "   msr basepri, r0                                 \n" /* Enable interrupts. */
 456             "                                                   \n"
 457             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 458             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 459             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 460             "                                                   \n"
 461             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
 462             "   msr psplim, r1                                  \n" /* Restore the PSPLIM register value for the task. */
 463             "   mov lr, r4                                      \n" /* LR = r4. */
 464             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 465             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
 466             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
 467             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 468             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 469             "   push {r2, r4}                                   \n"
 470             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 471             "   pop {r2, r4}                                    \n"
 472             "   mov lr, r4                                      \n" /* LR = r4. */
 473             "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 474             "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 475             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 476             "   bx lr                                           \n"
 477             "                                                   \n"
 478             " restore_ns_context:                               \n"
 479             "   ldmia r2!, {r4-r11}                             \n" /* Restore the registers that are not automatically restored. */
 480             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 481                 "   tst lr, #0x10                               \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 482                 "   it eq                                       \n"
 483                 "   vldmiaeq r2!, {s16-s31}                     \n" /* Restore the additional FP context registers which are not restored automatically. */
 484             #endif /* configENABLE_FPU || configENABLE_MVE */
 485             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 486             "   bx lr                                           \n"
 487             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 488         );
 489     }
 490
 491 #endif /* configENABLE_MPU */
 492 /*-----------------------------------------------------------*/
 493
 494 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 495
 496     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 497     {
 498         __asm volatile
 499         (
 500             ".syntax unified                \n"
 501             ".extern vPortSVCHandler_C      \n"
 502             ".extern vSystemCallEnter       \n"
 503             ".extern vSystemCallExit        \n"
 504             "                               \n"
 505             "tst lr, #4                     \n"
 506             "ite eq                         \n"
 507             "mrseq r0, msp                  \n"
 508             "mrsne r0, psp                  \n"
 509             "                               \n"
 510             "ldr r1, [r0, #24]              \n"
 511             "ldrb r2, [r1, #-2]             \n"
 512             "cmp r2, %0                     \n"
 513             "blt syscall_enter              \n"
 514             "cmp r2, %1                     \n"
 515             "beq syscall_exit               \n"
 516             "b vPortSVCHandler_C            \n"
 517             "                               \n"
 518             "syscall_enter:                 \n"
 519             "    mov r1, lr                 \n"
 520             "    b vSystemCallEnter         \n"
 521             "                               \n"
 522             "syscall_exit:                  \n"
 523             "    mov r1, lr                 \n"
 524             "    b vSystemCallExit          \n"
 525             "                               \n"
 526             : /* No outputs. */
 527             : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
 528             : "r0", "r1", "r2", "memory"
 529         );
 530     }
 531
 532 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 533
 534     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 535     {
 536         __asm volatile
 537         (
 538             "   .syntax unified                                 \n"
 539             "                                                   \n"
 540             "   tst lr, #4                                      \n"
 541             "   ite eq                                          \n"
 542             "   mrseq r0, msp                                   \n"
 543             "   mrsne r0, psp                                   \n"
 544             "   ldr r1, =vPortSVCHandler_C                      \n"
 545             "   bx r1                                           \n"
 546         );
 547     }
 548
 549 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 550 /*-----------------------------------------------------------*/
 551
 552 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 553 {
 554     __asm volatile
 555     (
 556         "   .syntax unified                                 \n"
 557         "                                                   \n"
 558         "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
 559         "   bx lr                                           \n" /* Return. */
 560         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
 561     );
 562 }
 563 /*-----------------------------------------------------------*/
 564
 565 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 566 {
 567     __asm volatile
 568     (
 569         "   .syntax unified                                 \n"
 570         "                                                   \n"
 571         "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
 572         "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
 573         "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
 574         "   it ne                                           \n"
 575         "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
 576         "   bx lr                                           \n" /* Return. */
 577         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
 578     );
 579 }
 580 /*-----------------------------------------------------------*/