begriffs open source - freertos/blob - portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c

   1 /*
   2  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   4  * Copyright 2024 Arm Limited and/or its affiliates
   5  * <open-source-office@arm.com>
   6  *
   7  * SPDX-License-Identifier: MIT
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  10  * this software and associated documentation files (the "Software"), to deal in
  11  * the Software without restriction, including without limitation the rights to
  12  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  13  * the Software, and to permit persons to whom the Software is furnished to do so,
  14  * subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in all
  17  * copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  21  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  22  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  23  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  24  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * https://www.FreeRTOS.org
  27  * https://github.com/FreeRTOS
  28  *
  29  */
  30
  31 /* Standard includes. */
  32 #include <stdint.h>
  33
  34 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  35  * is defined correctly and privileged functions are placed in correct sections. */
  36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  37
  38 /* Portasm includes. */
  39 #include "portasm.h"
  40
  41 /* System call numbers includes. */
  42 #include "mpu_syscall_numbers.h"
  43
  44 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  45  * header files. */
  46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  47
  48 #if ( configENABLE_MPU == 1 )
  49
  50     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  51     {
  52         __asm volatile
  53         (
  54             " .syntax unified                                 \n"
  55             "                                                 \n"
  56             " program_mpu_first_task:                         \n"
  57             "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  58             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
  59             "                                                 \n"
  60             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
  61             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  62             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  63             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
  64             "    str r2, [r1]                                 \n" /* Disable MPU. */
  65             "                                                 \n"
  66             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
  67             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
  68             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
  69             "    str r1, [r2]                                 \n" /* Program MAIR0. */
  70             "                                                 \n"
  71             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
  72             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
  73             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  74             "                                                 \n"
  75             "    movs r3, #4                                  \n" /* r3 = 4. */
  76             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
  77             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
  78             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  79             "                                                 \n"
  80             #if ( configTOTAL_MPU_REGIONS == 16 )
  81                 "    movs r3, #8                                  \n" /* r3 = 8. */
  82                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
  83                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
  84                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  85                 "    movs r3, #12                                 \n" /* r3 = 12. */
  86                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
  87                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
  88                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
  89             #endif /* configTOTAL_MPU_REGIONS == 16 */
  90             "                                                 \n"
  91             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  92             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
  93             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
  94             "   str r2, [r1]                                  \n" /* Enable MPU. */
  95             "   dsb                                           \n" /* Force memory writes before continuing. */
  96             "                                                 \n"
  97             " restore_context_first_task:                     \n"
  98             "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  99             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
 100             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
 101             "                                                 \n"
 102             " restore_special_regs_first_task:                \n"
 103             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
 104             "    msr psp, r2                                  \n"
 105             "    msr psplim, r3                               \n"
 106             "    msr control, r4                              \n"
 107             "                                                 \n"
 108             " restore_general_regs_first_task:                \n"
 109             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 110             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 111             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
 112             "                                                 \n"
 113             " restore_context_done_first_task:                \n"
 114             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 115             "    mov r0, #0                                   \n"
 116             "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
 117             "    bx lr                                        \n"
 118         );
 119     }
 120
 121 #else /* configENABLE_MPU */
 122
 123     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 124     {
 125         __asm volatile
 126         (
 127             "   .syntax unified                                 \n"
 128             "                                                   \n"
 129             "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 130             "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
 131             "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 132             "                                                   \n"
 133             "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
 134             "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
 135             "   mrs  r1, control                                \n" /* Obtain current control register value. */
 136             "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
 137             "   msr control, r1                                 \n" /* Write back the new control register value. */
 138             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
 139             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
 140             "   isb                                             \n"
 141             "   mov  r0, #0                                     \n"
 142             "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
 143             "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
 144         );
 145     }
 146
 147 #endif /* configENABLE_MPU */
 148 /*-----------------------------------------------------------*/
 149
 150 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 151 {
 152     __asm volatile
 153     (
 154         "   .syntax unified                                 \n"
 155         "                                                   \n"
 156         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 157         "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
 158         "   ite ne                                          \n"
 159         "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 160         "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 161         "   bx lr                                           \n" /* Return. */
 162         ::: "r0", "memory"
 163     );
 164 }
 165 /*-----------------------------------------------------------*/
 166
 167 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 168 {
 169     __asm volatile
 170     (
 171         "   .syntax unified                                 \n"
 172         "                                                   \n"
 173         "   mrs  r0, control                                \n" /* Read the CONTROL register. */
 174         "   bic r0, #1                                      \n" /* Clear the bit 0. */
 175         "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
 176         "   bx lr                                           \n" /* Return to the caller. */
 177         ::: "r0", "memory"
 178     );
 179 }
 180 /*-----------------------------------------------------------*/
 181
 182 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 183 {
 184     __asm volatile
 185     (
 186         "   .syntax unified                                 \n"
 187         "                                                   \n"
 188         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 189         "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
 190         "   msr control, r0                                 \n" /* CONTROL = r0. */
 191         "   bx lr                                           \n" /* Return to the caller. */
 192         ::: "r0", "memory"
 193     );
 194 }
 195 /*-----------------------------------------------------------*/
 196
 197 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 198 {
 199     __asm volatile
 200     (
 201         "   .syntax unified                                 \n"
 202         "                                                   \n"
 203         "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
 204         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
 205         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
 206         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
 207         "   cpsie i                                         \n" /* Globally enable interrupts. */
 208         "   cpsie f                                         \n"
 209         "   dsb                                             \n"
 210         "   isb                                             \n"
 211         "   svc %0                                          \n" /* System call to start the first task. */
 212         "   nop                                             \n"
 213         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 214     );
 215 }
 216 /*-----------------------------------------------------------*/
 217
 218 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 219 {
 220     __asm volatile
 221     (
 222         "   .syntax unified                                 \n"
 223         "                                                   \n"
 224         "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
 225         "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 226         "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 227         "   dsb                                             \n"
 228         "   isb                                             \n"
 229         "   bx lr                                           \n" /* Return. */
 230         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
 231     );
 232 }
 233 /*-----------------------------------------------------------*/
 234
 235 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 236 {
 237     __asm volatile
 238     (
 239         "   .syntax unified                                 \n"
 240         "                                                   \n"
 241         "   msr basepri, r0                                 \n" /* basepri = ulMask. */
 242         "   dsb                                             \n"
 243         "   isb                                             \n"
 244         "   bx lr                                           \n" /* Return. */
 245         ::: "memory"
 246     );
 247 }
 248 /*-----------------------------------------------------------*/
 249
 250 #if ( configENABLE_MPU == 1 )
 251
 252     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 253     {
 254         __asm volatile
 255         (
 256             " .syntax unified                                 \n"
 257             "                                                 \n"
 258             " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 259             " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
 260             " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
 261             " mrs r2, psp                                     \n" /* r2 = PSP. */
 262             "                                                 \n"
 263             " save_general_regs:                              \n"
 264             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 265                 "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
 266                 "    tst lr, #0x10                                \n"
 267                 "    ittt eq                                      \n"
 268                 "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
 269                 "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
 270                 "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
 271                 "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
 272             #endif /* configENABLE_FPU || configENABLE_MVE */
 273             "                                                 \n"
 274             "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
 275             "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
 276             "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
 277             "                                                 \n"
 278             " save_special_regs:                              \n"
 279             "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
 280             "    mrs r4, control                              \n" /* r4 = CONTROL. */
 281             "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
 282             "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
 283             "                                                 \n"
 284             " select_next_task:                               \n"
 285             "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 286             "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 287             "    dsb                                          \n"
 288             "    isb                                          \n"
 289             "    bl vTaskSwitchContext                        \n"
 290             "    mov r0, #0                                   \n" /* r0 = 0. */
 291             "    msr basepri, r0                              \n" /* Enable interrupts. */
 292             "                                                 \n"
 293             " program_mpu:                                    \n"
 294             "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 295             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
 296             "                                                 \n"
 297             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
 298             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 299             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 300             "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
 301             "    str r2, [r1]                                 \n" /* Disable MPU. */
 302             "                                                 \n"
 303             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
 304             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
 305             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
 306             "    str r1, [r2]                                 \n" /* Program MAIR0. */
 307             "                                                 \n"
 308             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
 309             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
 310             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 311             "                                                 \n"
 312             "    movs r3, #4                                  \n" /* r3 = 4. */
 313             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
 314             "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 315             "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 316             "                                                 \n"
 317             #if ( configTOTAL_MPU_REGIONS == 16 )
 318                 "    movs r3, #8                                  \n" /* r3 = 8. */
 319                 "    str r3, [r1]                                 \n" /* Program RNR = 8. */
 320                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 321                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 322                 "    movs r3, #12                                 \n" /* r3 = 12. */
 323                 "    str r3, [r1]                                 \n" /* Program RNR = 12. */
 324                 "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
 325                 "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
 326             #endif /* configTOTAL_MPU_REGIONS == 16 */
 327             "                                                 \n"
 328             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 329             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
 330             "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
 331             "   str r2, [r1]                                  \n" /* Enable MPU. */
 332             "   dsb                                           \n" /* Force memory writes before continuing. */
 333             "                                                 \n"
 334             " restore_context:                                \n"
 335             "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 336             "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
 337             "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
 338             "                                                 \n"
 339             " restore_special_regs:                           \n"
 340             "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
 341             "    msr psp, r2                                  \n"
 342             "    msr psplim, r3                               \n"
 343             "    msr control, r4                              \n"
 344             "                                                 \n"
 345             " restore_general_regs:                           \n"
 346             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
 347             "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
 348             "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
 349             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 350                 "    tst lr, #0x10                                \n"
 351                 "    ittt eq                                      \n"
 352                 "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
 353                 "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
 354                 "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
 355             #endif /* configENABLE_FPU || configENABLE_MVE */
 356             "                                                 \n"
 357             " restore_context_done:                           \n"
 358             "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 359             "    bx lr                                        \n"
 360             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 361         );
 362     }
 363
 364 #else /* configENABLE_MPU */
 365
 366     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 367     {
 368         __asm volatile
 369         (
 370             "   .syntax unified                                 \n"
 371             "                                                   \n"
 372             "   mrs r0, psp                                     \n" /* Read PSP in r0. */
 373             "                                                   \n"
 374             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 375                 "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 376                 "   it eq                                           \n"
 377                 "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
 378             #endif /* configENABLE_FPU || configENABLE_MVE */
 379             "                                                   \n"
 380             "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
 381             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 382             "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
 383             "                                                   \n"
 384             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 385             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
 386             "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
 387             "                                                   \n"
 388             "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
 389             "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 390             "   dsb                                             \n"
 391             "   isb                                             \n"
 392             "   bl vTaskSwitchContext                           \n"
 393             "   mov r0, #0                                      \n" /* r0 = 0. */
 394             "   msr basepri, r0                                 \n" /* Enable interrupts. */
 395             "                                                   \n"
 396             "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 397             "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
 398             "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 399             "                                                   \n"
 400             "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 401             "                                                   \n"
 402             #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 403                 "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 404                 "   it eq                                           \n"
 405                 "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
 406             #endif /* configENABLE_FPU || configENABLE_MVE */
 407             "                                                   \n"
 408             "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
 409             "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
 410             "   bx r3                                           \n"
 411             ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
 412         );
 413     }
 414
 415 #endif /* configENABLE_MPU */
 416 /*-----------------------------------------------------------*/
 417
 418 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 419
 420     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 421     {
 422         __asm volatile
 423         (
 424             ".syntax unified                \n"
 425             ".extern vPortSVCHandler_C      \n"
 426             ".extern vSystemCallEnter       \n"
 427             ".extern vSystemCallExit        \n"
 428             "                               \n"
 429             "tst lr, #4                     \n"
 430             "ite eq                         \n"
 431             "mrseq r0, msp                  \n"
 432             "mrsne r0, psp                  \n"
 433             "                               \n"
 434             "ldr r1, [r0, #24]              \n"
 435             "ldrb r2, [r1, #-2]             \n"
 436             "cmp r2, %0                     \n"
 437             "blt syscall_enter              \n"
 438             "cmp r2, %1                     \n"
 439             "beq syscall_exit               \n"
 440             "b vPortSVCHandler_C            \n"
 441             "                               \n"
 442             "syscall_enter:                 \n"
 443             "    mov r1, lr                 \n"
 444             "    b vSystemCallEnter         \n"
 445             "                               \n"
 446             "syscall_exit:                  \n"
 447             "    mov r1, lr                 \n"
 448             "    b vSystemCallExit          \n"
 449             "                               \n"
 450             : /* No outputs. */
 451             : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
 452             : "r0", "r1", "r2", "memory"
 453         );
 454     }
 455
 456 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 457
 458     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 459     {
 460         __asm volatile
 461         (
 462             "   .syntax unified                                 \n"
 463             "                                                   \n"
 464             "   tst lr, #4                                      \n"
 465             "   ite eq                                          \n"
 466             "   mrseq r0, msp                                   \n"
 467             "   mrsne r0, psp                                   \n"
 468             "   ldr r1, =vPortSVCHandler_C                      \n"
 469             "   bx r1                                           \n"
 470         );
 471     }
 472
 473 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 474 /*-----------------------------------------------------------*/