begriffs open source - freertos/blob - portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel V10.5.1\r
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * SPDX-License-Identifier: MIT\r
   6  *\r
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   8  * this software and associated documentation files (the "Software"), to deal in\r
   9  * the Software without restriction, including without limitation the rights to\r
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
  11  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  12  * subject to the following conditions:\r
  13  *\r
  14  * The above copyright notice and this permission notice shall be included in all\r
  15  * copies or substantial portions of the Software.\r
  16  *\r
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  23  *\r
  24  * https://www.FreeRTOS.org\r
  25  * https://github.com/FreeRTOS\r
  26  *\r
  27  */\r
  28 \r
  29 /* Standard includes. */\r
  30 #include <stdint.h>\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
  33  * is defined correctly and privileged functions are placed in correct sections. */\r
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  35 \r
  36 /* Portasm includes. */\r
  37 #include "portasm.h"\r
  38 \r
  39 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
  40  * header files. */\r
  41 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  42 \r
  43 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  44 {\r
  45     __asm volatile\r
  46     (\r
  47         "       .syntax unified                                                                 \n"\r
  48         "                                                                                                       \n"\r
  49         "       ldr  r2, pxCurrentTCBConst2                                             \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  50         "       ldr  r1, [r2]                                                                   \n"/* Read pxCurrentTCB. */\r
  51         "       ldr  r0, [r1]                                                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  52         "                                                                                                       \n"\r
  53         #if ( configENABLE_MPU == 1 )\r
  54             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
  55             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  56             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  57             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  58             "   str r4, [r2]                                                                    \n"/* Disable MPU. */\r
  59             "                                                                                                   \n"\r
  60             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  61             "   ldr  r3, [r1]                                                                   \n"/* r3 = *r1 i.e. r3 = MAIR0. */\r
  62             "   ldr  r2, xMAIR0Const2                                                   \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  63             "   str  r3, [r2]                                                                   \n"/* Program MAIR0. */\r
  64             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
  65             "   movs r3, #4                                                                             \n"/* r3 = 4. */\r
  66             "   str  r3, [r2]                                                                   \n"/* Program RNR = 4. */\r
  67             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  68             "   ldr  r2, xRBARConst2                                                    \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
  69             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 set of RBAR/RLAR registers from TCB. */\r
  70             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  71             "                                                                                                   \n"\r
  72             #if ( configTOTAL_MPU_REGIONS == 16 )\r
  73             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
  74             "   movs r3, #8                                                                             \n"/* r3 = 8. */\r
  75             "   str  r3, [r2]                                                                   \n"/* Program RNR = 8. */\r
  76             "   ldr  r2, xRBARConst2                                                    \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
  77             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 set of RBAR/RLAR registers from TCB. */\r
  78             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  79             "   ldr  r2, xRNRConst2                                                             \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
  80             "   movs r3, #12                                                                    \n"/* r3 = 12. */\r
  81             "   str  r3, [r2]                                                                   \n"/* Program RNR = 12. */\r
  82             "   ldr  r2, xRBARConst2                                                    \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
  83             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 set of RBAR/RLAR registers from TCB. */\r
  84             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  85             #endif /* configTOTAL_MPU_REGIONS == 16 */\r
  86             "                                                                                                   \n"\r
  87             "   ldr r2, xMPUCTRLConst2                                                  \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  88             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
  89             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
  90             "   str r4, [r2]                                                                    \n"/* Enable MPU. */\r
  91             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
  92         #endif /* configENABLE_MPU */\r
  93         "                                                                                                       \n"\r
  94         #if ( configENABLE_MPU == 1 )\r
  95             "   ldm  r0!, {r1-r3}                                                               \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
  96             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
  97             "   msr  control, r2                                                                \n"/* Set this task's CONTROL value. */\r
  98             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
  99             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
 100             "   isb                                                                                             \n"\r
 101             "   mov  r0, #0                                                                             \n"\r
 102             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */\r
 103             "   bx   r3                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
 104         #else /* configENABLE_MPU */\r
 105             "   ldm  r0!, {r1-r2}                                                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 106             "   msr  psplim, r1                                                                 \n"/* Set this task's PSPLIM value. */\r
 107             "   movs r1, #2                                                                             \n"/* r1 = 2. */\r
 108             "   msr  CONTROL, r1                                                                \n"/* Switch to use PSP in the thread mode. */\r
 109             "   adds r0, #32                                                                    \n"/* Discard everything up to r0. */\r
 110             "   msr  psp, r0                                                                    \n"/* This is now the new top of stack to use in the task. */\r
 111             "   isb                                                                                             \n"\r
 112             "   mov  r0, #0                                                                             \n"\r
 113             "   msr  basepri, r0                                                                \n"/* Ensure that interrupts are enabled when the first task starts. */\r
 114             "   bx   r2                                                                                 \n"/* Finally, branch to EXC_RETURN. */\r
 115         #endif /* configENABLE_MPU */\r
 116         "                                                                                                       \n"\r
 117         "       .align 4                                                                                \n"\r
 118         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 119         #if ( configENABLE_MPU == 1 )\r
 120             "xMPUCTRLConst2: .word 0xe000ed94                                   \n"\r
 121             "xMAIR0Const2: .word 0xe000edc0                                             \n"\r
 122             "xRNRConst2: .word 0xe000ed98                                               \n"\r
 123             "xRBARConst2: .word 0xe000ed9c                                              \n"\r
 124         #endif /* configENABLE_MPU */\r
 125     );\r
 126 }\r
 127 /*-----------------------------------------------------------*/\r
 128 \r
 129 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 130 {\r
 131     __asm volatile\r
 132     (\r
 133         "       .syntax unified                                                                 \n"\r
 134         "                                                                                                       \n"\r
 135         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 136         "       tst r0, #1                                                                              \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 137         "       ite ne                                                                                  \n"\r
 138         "       movne r0, #0                                                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 139         "       moveq r0, #1                                                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 140         "       bx lr                                                                                   \n"/* Return. */\r
 141         "                                                                                                       \n"\r
 142         "       .align 4                                                                                \n"\r
 143         ::: "r0", "memory"\r
 144     );\r
 145 }\r
 146 /*-----------------------------------------------------------*/\r
 147 \r
 148 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 149 {\r
 150     __asm volatile\r
 151     (\r
 152         "       .syntax unified                                                                 \n"\r
 153         "                                                                                                       \n"\r
 154         "       mrs  r0, control                                                                \n"/* Read the CONTROL register. */\r
 155         "       bic r0, #1                                                                              \n"/* Clear the bit 0. */\r
 156         "       msr  control, r0                                                                \n"/* Write back the new CONTROL value. */\r
 157         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 158         ::: "r0", "memory"\r
 159     );\r
 160 }\r
 161 /*-----------------------------------------------------------*/\r
 162 \r
 163 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 164 {\r
 165     __asm volatile\r
 166     (\r
 167         "       .syntax unified                                                                 \n"\r
 168         "                                                                                                       \n"\r
 169         "       mrs r0, control                                                                 \n"/* r0 = CONTROL. */\r
 170         "       orr r0, #1                                                                              \n"/* r0 = r0 | 1. */\r
 171         "       msr control, r0                                                                 \n"/* CONTROL = r0. */\r
 172         "       bx lr                                                                                   \n"/* Return to the caller. */\r
 173         ::: "r0", "memory"\r
 174     );\r
 175 }\r
 176 /*-----------------------------------------------------------*/\r
 177 \r
 178 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 179 {\r
 180     __asm volatile\r
 181     (\r
 182         "       .syntax unified                                                                 \n"\r
 183         "                                                                                                       \n"\r
 184         "       ldr r0, xVTORConst                                                              \n"/* Use the NVIC offset register to locate the stack. */\r
 185         "       ldr r0, [r0]                                                                    \n"/* Read the VTOR register which gives the address of vector table. */\r
 186         "       ldr r0, [r0]                                                                    \n"/* The first entry in vector table is stack pointer. */\r
 187         "       msr msp, r0                                                                             \n"/* Set the MSP back to the start of the stack. */\r
 188         "       cpsie i                                                                                 \n"/* Globally enable interrupts. */\r
 189         "       cpsie f                                                                                 \n"\r
 190         "       dsb                                                                                             \n"\r
 191         "       isb                                                                                             \n"\r
 192         "       svc %0                                                                                  \n"/* System call to start the first task. */\r
 193         "       nop                                                                                             \n"\r
 194         "                                                                                                       \n"\r
 195         "   .align 4                                                                            \n"\r
 196         "xVTORConst: .word 0xe000ed08                                           \n"\r
 197         ::"i" ( portSVC_START_SCHEDULER ) : "memory"\r
 198     );\r
 199 }\r
 200 /*-----------------------------------------------------------*/\r
 201 \r
 202 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 203 {\r
 204     __asm volatile\r
 205     (\r
 206         "       .syntax unified                                                                 \n"\r
 207         "                                                                                                       \n"\r
 208         "       mrs r0, basepri                                                                 \n"/* r0 = basepri. Return original basepri value. */\r
 209         "       mov r1, %0                                                                              \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 210         "       msr basepri, r1                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 211         "       dsb                                                                                             \n"\r
 212         "       isb                                                                                             \n"\r
 213         "       bx lr                                                                                   \n"/* Return. */\r
 214         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
 215     );\r
 216 }\r
 217 /*-----------------------------------------------------------*/\r
 218 \r
 219 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 220 {\r
 221     __asm volatile\r
 222     (\r
 223         "       .syntax unified                                                                 \n"\r
 224         "                                                                                                       \n"\r
 225         "       msr basepri, r0                                                                 \n"/* basepri = ulMask. */\r
 226         "       dsb                                                                                             \n"\r
 227         "       isb                                                                                             \n"\r
 228         "       bx lr                                                                                   \n"/* Return. */\r
 229         ::: "memory"\r
 230     );\r
 231 }\r
 232 /*-----------------------------------------------------------*/\r
 233 \r
 234 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 235 {\r
 236     __asm volatile\r
 237     (\r
 238         "       .syntax unified                                                                 \n"\r
 239         "                                                                                                       \n"\r
 240         "       mrs r0, psp                                                                             \n"/* Read PSP in r0. */\r
 241         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\r
 242             "   tst lr, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\r
 243             "   it eq                                                                                   \n"\r
 244             "   vstmdbeq r0!, {s16-s31}                                                 \n"/* Store the additional FP context registers which are not saved automatically. */\r
 245         #endif /* configENABLE_FPU || configENABLE_MVE */\r
 246         #if ( configENABLE_MPU == 1 )\r
 247             "   mrs r1, psplim                                                                  \n"/* r1 = PSPLIM. */\r
 248             "   mrs r2, control                                                                 \n"/* r2 = CONTROL. */\r
 249             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 250             "   stmdb r0!, {r1-r11}                                                             \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 251         #else /* configENABLE_MPU */\r
 252             "   mrs r2, psplim                                                                  \n"/* r2 = PSPLIM. */\r
 253             "   mov r3, lr                                                                              \n"/* r3 = LR/EXC_RETURN. */\r
 254             "   stmdb r0!, {r2-r11}                                                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
 255         #endif /* configENABLE_MPU */\r
 256         "                                                                                                       \n"\r
 257         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 258         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 259         "       str r0, [r1]                                                                    \n"/* Save the new top of stack in TCB. */\r
 260         "                                                                                                       \n"\r
 261         "       mov r0, %0                                                                              \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
 262         "       msr basepri, r0                                                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 263         "       dsb                                                                                             \n"\r
 264         "       isb                                                                                             \n"\r
 265         "       bl vTaskSwitchContext                                                   \n"\r
 266         "       mov r0, #0                                                                              \n"/* r0 = 0. */\r
 267         "       msr basepri, r0                                                                 \n"/* Enable interrupts. */\r
 268         "                                                                                                       \n"\r
 269         "       ldr r2, pxCurrentTCBConst                                               \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 270         "       ldr r1, [r2]                                                                    \n"/* Read pxCurrentTCB. */\r
 271         "       ldr r0, [r1]                                                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 272         "                                                                                                       \n"\r
 273         #if ( configENABLE_MPU == 1 )\r
 274             "   dmb                                                                                             \n"/* Complete outstanding transfers before disabling MPU. */\r
 275             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 276             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 277             "   bic r4, #1                                                                              \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 278             "   str r4, [r2]                                                                    \n"/* Disable MPU. */\r
 279             "                                                                                                   \n"\r
 280             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 281             "   ldr r3, [r1]                                                                    \n"/* r3 = *r1 i.e. r3 = MAIR0. */\r
 282             "   ldr r2, xMAIR0Const                                                             \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 283             "   str r3, [r2]                                                                    \n"/* Program MAIR0. */\r
 284             "   ldr r2, xRNRConst                                                               \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
 285             "   movs r3, #4                                                                             \n"/* r3 = 4. */\r
 286             "   str r3, [r2]                                                                    \n"/* Program RNR = 4. */\r
 287             "   adds r1, #4                                                                             \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 288             "   ldr r2, xRBARConst                                                              \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
 289             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 290             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 291             "                                                                                                   \n"\r
 292             #if ( configTOTAL_MPU_REGIONS == 16 )\r
 293             "   ldr r2, xRNRConst                                                               \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
 294             "   movs r3, #8                                                                             \n"/* r3 = 8. */\r
 295             "   str r3, [r2]                                                                    \n"/* Program RNR = 8. */\r
 296             "   ldr r2, xRBARConst                                                              \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
 297             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 298             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 299             "   ldr r2, xRNRConst                                                               \n"/* r2 = 0xe000ed98 [Location of RNR]. */\r
 300             "   movs r3, #12                                                                    \n"/* r3 = 12. */\r
 301             "   str r3, [r2]                                                                    \n"/* Program RNR = 12. */\r
 302             "   ldr r2, xRBARConst                                                              \n"/* r2 = 0xe000ed9c [Location of RBAR]. */\r
 303             "   ldmia r1!, {r4-r11}                                                             \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 304             "   stmia r2!, {r4-r11}                                                             \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 305             #endif /* configTOTAL_MPU_REGIONS == 16 */\r
 306             "                                                                                                   \n"\r
 307             "   ldr r2, xMPUCTRLConst                                                   \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 308             "   ldr r4, [r2]                                                                    \n"/* Read the value of MPU_CTRL. */\r
 309             "   orr r4, #1                                                                              \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 310             "   str r4, [r2]                                                                    \n"/* Enable MPU. */\r
 311             "   dsb                                                                                             \n"/* Force memory writes before continuing. */\r
 312         #endif /* configENABLE_MPU */\r
 313         "                                                                                                       \n"\r
 314         #if ( configENABLE_MPU == 1 )\r
 315             "   ldmia r0!, {r1-r11}                                                             \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 316         #else /* configENABLE_MPU */\r
 317             "   ldmia r0!, {r2-r11}                                                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 318         #endif /* configENABLE_MPU */\r
 319         "                                                                                                       \n"\r
 320         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )\r
 321             "   tst r3, #0x10                                                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */\r
 322             "   it eq                                                                                   \n"\r
 323             "   vldmiaeq r0!, {s16-s31}                                                 \n"/* Restore the additional FP context registers which are not restored automatically. */\r
 324         #endif /* configENABLE_FPU || configENABLE_MVE */\r
 325         "                                                                                                       \n"\r
 326         #if ( configENABLE_MPU == 1 )\r
 327             "   msr psplim, r1                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 328             "   msr control, r2                                                                 \n"/* Restore the CONTROL register value for the task. */\r
 329         #else /* configENABLE_MPU */\r
 330             "   msr psplim, r2                                                                  \n"/* Restore the PSPLIM register value for the task. */\r
 331         #endif /* configENABLE_MPU */\r
 332         "       msr psp, r0                                                                             \n"/* Remember the new top of stack for the task. */\r
 333         "       bx r3                                                                                   \n"\r
 334         "                                                                                                       \n"\r
 335         "       .align 4                                                                                \n"\r
 336         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 337         #if ( configENABLE_MPU == 1 )\r
 338             "xMPUCTRLConst: .word 0xe000ed94                                    \n"\r
 339             "xMAIR0Const: .word 0xe000edc0                                              \n"\r
 340             "xRNRConst: .word 0xe000ed98                                                \n"\r
 341             "xRBARConst: .word 0xe000ed9c                                               \n"\r
 342         #endif /* configENABLE_MPU */\r
 343         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
 344     );\r
 345 }\r
 346 /*-----------------------------------------------------------*/\r
 347 \r
 348 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 349 {\r
 350     __asm volatile\r
 351     (\r
 352         "       .syntax unified                                                                 \n"\r
 353         "                                                                                                       \n"\r
 354         "       tst lr, #4                                                                              \n"\r
 355         "       ite eq                                                                                  \n"\r
 356         "       mrseq r0, msp                                                                   \n"\r
 357         "       mrsne r0, psp                                                                   \n"\r
 358         "       ldr r1, svchandler_address_const                                \n"\r
 359         "       bx r1                                                                                   \n"\r
 360         "                                                                                                       \n"\r
 361         "       .align 4                                                                                \n"\r
 362         "svchandler_address_const: .word vPortSVCHandler_C      \n"\r
 363     );\r
 364 }\r
 365 /*-----------------------------------------------------------*/\r