begriffs open source - freertos/blob - portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel V10.4.3 LTS Patch 1\r
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * https://www.FreeRTOS.org\r
  23  * https://github.com/FreeRTOS\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 /* Including FreeRTOSConfig.h here will cause build errors if the header file\r
  28 contains code not understood by the assembler - for example the 'extern' keyword.\r
  29 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
  30 the code is included in C files but excluded by the preprocessor in assembly\r
  31 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
  32 #include "FreeRTOSConfig.h"\r
  33 \r
  34         EXTERN pxCurrentTCB\r
  35         EXTERN vTaskSwitchContext\r
  36         EXTERN vPortSVCHandler_C\r
  37 \r
  38         PUBLIC xIsPrivileged\r
  39         PUBLIC vResetPrivilege\r
  40         PUBLIC vRestoreContextOfFirstTask\r
  41         PUBLIC vRaisePrivilege\r
  42         PUBLIC vStartFirstTask\r
  43         PUBLIC ulSetInterruptMask\r
  44         PUBLIC vClearInterruptMask\r
  45         PUBLIC PendSV_Handler\r
  46         PUBLIC SVC_Handler\r
  47 /*-----------------------------------------------------------*/\r
  48 \r
  49 /*---------------- Unprivileged Functions -------------------*/\r
  50 \r
  51 /*-----------------------------------------------------------*/\r
  52 \r
  53         SECTION .text:CODE:NOROOT(2)\r
  54         THUMB\r
  55 /*-----------------------------------------------------------*/\r
  56 \r
  57 xIsPrivileged:\r
  58         mrs r0, control                                                 /* r0 = CONTROL. */\r
  59         tst r0, #1                                                              /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
  60         ite ne\r
  61         movne r0, #0                                                    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  62         moveq r0, #1                                                    /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
  63         bx lr                                                                   /* Return. */\r
  64 /*-----------------------------------------------------------*/\r
  65 \r
  66 vResetPrivilege:\r
  67         mrs r0, control                                                 /* r0 = CONTROL. */\r
  68         orr r0, r0, #1                                                  /* r0 = r0 | 1. */\r
  69         msr control, r0                                                 /* CONTROL = r0. */\r
  70         bx lr                                                                   /* Return to the caller. */\r
  71 /*-----------------------------------------------------------*/\r
  72 \r
  73 /*----------------- Privileged Functions --------------------*/\r
  74 \r
  75 /*-----------------------------------------------------------*/\r
  76 \r
  77         SECTION privileged_functions:CODE:NOROOT(2)\r
  78         THUMB\r
  79 /*-----------------------------------------------------------*/\r
  80 \r
  81 vRestoreContextOfFirstTask:\r
  82         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  83         ldr  r1, [r2]                                                   /* Read pxCurrentTCB. */\r
  84         ldr  r0, [r1]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  85 \r
  86 #if ( configENABLE_MPU == 1 )\r
  87         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
  88         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  89         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
  90         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  91         str r4, [r2]                                                    /* Disable MPU. */\r
  92 \r
  93         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  94         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
  95         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  96         str r3, [r2]                                                    /* Program MAIR0. */\r
  97         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
  98         movs r3, #4                                                             /* r3 = 4. */\r
  99         str r3, [r2]                                                    /* Program RNR = 4. */\r
 100         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 101         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 102         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 103         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 104 \r
 105         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 106         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 107         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 108         str r4, [r2]                                                    /* Enable MPU. */\r
 109         dsb                                                                             /* Force memory writes before continuing. */\r
 110 #endif /* configENABLE_MPU */\r
 111 \r
 112 #if ( configENABLE_MPU == 1 )\r
 113         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
 114         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 115         msr  control, r2                                                /* Set this task's CONTROL value. */\r
 116         adds r0, #32                                                    /* Discard everything up to r0. */\r
 117         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 118         isb\r
 119         mov  r0, #0\r
 120         msr  basepri, r0                                                /* Ensure that interrupts are enabled when the first task starts. */\r
 121         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 122 #else /* configENABLE_MPU */\r
 123         ldm  r0!, {r1-r2}                                               /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 124         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 125         movs r1, #2                                                             /* r1 = 2. */\r
 126         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 127         adds r0, #32                                                    /* Discard everything up to r0. */\r
 128         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 129         isb\r
 130         mov  r0, #0\r
 131         msr  basepri, r0                                                /* Ensure that interrupts are enabled when the first task starts. */\r
 132         bx   r2                                                                 /* Finally, branch to EXC_RETURN. */\r
 133 #endif /* configENABLE_MPU */\r
 134 /*-----------------------------------------------------------*/\r
 135 \r
 136 vRaisePrivilege:\r
 137         mrs  r0, control                                                /* Read the CONTROL register. */\r
 138         bic r0, r0, #1                                                  /* Clear the bit 0. */\r
 139         msr  control, r0                                                /* Write back the new CONTROL value. */\r
 140         bx lr                                                                   /* Return to the caller. */\r
 141 /*-----------------------------------------------------------*/\r
 142 \r
 143 vStartFirstTask:\r
 144         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 145         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 146         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 147         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 148         cpsie i                                                                 /* Globally enable interrupts. */\r
 149         cpsie f\r
 150         dsb\r
 151         isb\r
 152         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 153 /*-----------------------------------------------------------*/\r
 154 \r
 155 ulSetInterruptMask:\r
 156         mrs r0, basepri                                                 /* r0 = basepri. Return original basepri value. */\r
 157         mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 158         msr basepri, r1                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 159         dsb\r
 160         isb\r
 161         bx lr                                                                   /* Return. */\r
 162 /*-----------------------------------------------------------*/\r
 163 \r
 164 vClearInterruptMask:\r
 165         msr basepri, r0                                                 /* basepri = ulMask. */\r
 166         dsb\r
 167         isb\r
 168         bx lr                                                                   /* Return. */\r
 169 /*-----------------------------------------------------------*/\r
 170 \r
 171 PendSV_Handler:\r
 172         mrs r0, psp                                                             /* Read PSP in r0. */\r
 173 #if ( configENABLE_FPU == 1 )\r
 174         tst lr, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 175         it eq\r
 176         vstmdbeq r0!, {s16-s31}                                 /* Store the FPU registers which are not saved automatically. */\r
 177 #endif /* configENABLE_FPU */\r
 178 #if ( configENABLE_MPU == 1 )\r
 179         mrs r1, psplim                                                  /* r1 = PSPLIM. */\r
 180         mrs r2, control                                                 /* r2 = CONTROL. */\r
 181         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 182         stmdb r0!, {r1-r11}                                             /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 183 #else /* configENABLE_MPU */\r
 184         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 185         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 186         stmdb r0!, {r2-r11}                                             /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
 187 #endif /* configENABLE_MPU */\r
 188 \r
 189         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 190         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 191         str r0, [r1]                                                    /* Save the new top of stack in TCB. */\r
 192 \r
 193         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 194         msr basepri, r0                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 195         dsb\r
 196         isb\r
 197         bl vTaskSwitchContext\r
 198         mov r0, #0                                                              /* r0 = 0. */\r
 199         msr basepri, r0                                                 /* Enable interrupts. */\r
 200 \r
 201         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 202         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 203         ldr r0, [r1]                                                    /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 204 \r
 205 #if ( configENABLE_MPU == 1 )\r
 206         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
 207         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 208         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 209         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 210         str r4, [r2]                                                    /* Disable MPU. */\r
 211 \r
 212         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 213         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
 214         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 215         str r3, [r2]                                                    /* Program MAIR0. */\r
 216         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
 217         movs r3, #4                                                             /* r3 = 4. */\r
 218         str r3, [r2]                                                    /* Program RNR = 4. */\r
 219         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 220         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 221         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 222         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 223 \r
 224         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 225         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 226         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 227         str r4, [r2]                                                    /* Enable MPU. */\r
 228         dsb                                                                             /* Force memory writes before continuing. */\r
 229 #endif /* configENABLE_MPU */\r
 230 \r
 231 #if ( configENABLE_MPU == 1 )\r
 232         ldmia r0!, {r1-r11}                                             /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 233 #else /* configENABLE_MPU */\r
 234         ldmia r0!, {r2-r11}                                             /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 235 #endif /* configENABLE_MPU */\r
 236 \r
 237 #if ( configENABLE_FPU == 1 )\r
 238         tst r3, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 239         it eq\r
 240         vldmiaeq r0!, {s16-s31}                                 /* Restore the FPU registers which are not restored automatically. */\r
 241 #endif /* configENABLE_FPU */\r
 242 \r
 243  #if ( configENABLE_MPU == 1 )\r
 244         msr psplim, r1                                                  /* Restore the PSPLIM register value for the task. */\r
 245         msr control, r2                                                 /* Restore the CONTROL register value for the task. */\r
 246 #else /* configENABLE_MPU */\r
 247         msr psplim, r2                                                  /* Restore the PSPLIM register value for the task. */\r
 248 #endif /* configENABLE_MPU */\r
 249         msr psp, r0                                                             /* Remember the new top of stack for the task. */\r
 250         bx r3\r
 251 /*-----------------------------------------------------------*/\r
 252 \r
 253 SVC_Handler:\r
 254         tst lr, #4\r
 255         ite eq\r
 256         mrseq r0, msp\r
 257         mrsne r0, psp\r
 258         b vPortSVCHandler_C\r
 259 /*-----------------------------------------------------------*/\r
 260 \r
 261         END\r