begriffs open source - freertos/blob - portable/GCC/ARM7

1 /*

2 * FreeRTOS SMP Kernel V202110.00

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a copy of

6 * this software and associated documentation files (the "Software"), to deal in

7 * the Software without restriction, including without limitation the rights to

8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of

9 * the Software, and to permit persons to whom the Software is furnished to do so,

10 * subject to the following conditions:

11 *

12 * The above copyright notice and this permission notice shall be included in all

13 * copies or substantial portions of the Software.

14 *

15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS

17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR

18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER

19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

21 *

22 * https://www.FreeRTOS.org

23 * https://github.com/FreeRTOS

24 *

25 * 1 tab == 4 spaces!

26 */

27

28

29 /*-----------------------------------------------------------

30 * Implementation of functions defined in portable.h for the ARM7 port.

31 *

32 * Components that can be compiled to either ARM or THUMB mode are

33 * contained in this file. The ISR routines, which can only be compiled

34 * to ARM mode are contained in portISR.c.

35 *----------------------------------------------------------*/

36

37 /* Standard includes. */

38 #include <stdlib.h>

39

40 /* Scheduler includes. */

41 #include "FreeRTOS.h"

42 #include "task.h"

43

44 /* Processor constants. */

45 #include "AT91SAM7X256.h"

46

47 /* Constants required to setup the task context. */

48 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */

49 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )

50 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )

51 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )

52

53 /* Constants required to setup the tick ISR. */

54 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )

55 #define portPRESCALE_VALUE 0x00

56 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )

57 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )

58

59 /* Constants required to setup the PIT. */

60 #define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 )

61 #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )

62

63 #define portINT_LEVEL_SENSITIVE 0

64 #define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 )

65 #define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 )

66 /*-----------------------------------------------------------*/

67

68 /* Setup the timer to generate the tick interrupts. */

69 static void prvSetupTimerInterrupt( void );

70

71 /*

72 * The scheduler can only be started from ARM mode, so

73 * vPortISRStartFirstSTask() is defined in portISR.c.

74 */

75 extern void vPortISRStartFirstTask( void );

76

77 /*-----------------------------------------------------------*/

78

79 /*

80 * Initialise the stack of a task to look exactly as if a call to

81 * portSAVE_CONTEXT had been called.

82 *

83 * See header file for description.

84 */

85 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )

86 {

87 StackType_t *pxOriginalTOS;

88

89 pxOriginalTOS = pxTopOfStack;

90

91 /* To ensure asserts in tasks.c don't fail, although in this case the assert

92 is not really required. */

93 pxTopOfStack--;

94

95 /* Setup the initial stack of the task. The stack is set exactly as

96 expected by the portRESTORE_CONTEXT() macro. */

97

98 /* First on the stack is the return address - which in this case is the

99 start of the task. The offset is added to make the return address appear

100 as it would within an IRQ ISR. */

101 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;

102 pxTopOfStack--;

103

104 *pxTopOfStack = ( StackType_t ) 0x00000000; /* R14 */

105 pxTopOfStack--;

106 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */

107 pxTopOfStack--;

108 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */

109 pxTopOfStack--;

110 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */

111 pxTopOfStack--;

112 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */

113 pxTopOfStack--;

114 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */

115 pxTopOfStack--;

116 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */

117 pxTopOfStack--;

118 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */

119 pxTopOfStack--;

120 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */

121 pxTopOfStack--;

122 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */

123 pxTopOfStack--;

124 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */

125 pxTopOfStack--;

126 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */

127 pxTopOfStack--;

128 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */

129 pxTopOfStack--;

130 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */

131 pxTopOfStack--;

132

133 /* When the task starts is will expect to find the function parameter in

134 R0. */

135 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */

136 pxTopOfStack--;

137

138 /* The last thing onto the stack is the status register, which is set for

139 system mode, with interrupts enabled. */

140 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;

141

142 #ifdef THUMB_INTERWORK

143 {

144 /* We want the task to start in thumb mode. */

145 *pxTopOfStack |= portTHUMB_MODE_BIT;

146 }

147 #endif

148

149 pxTopOfStack--;

150

151 /* Some optimisation levels use the stack differently to others. This

152 means the interrupt flags cannot always be stored on the stack and will

153 instead be stored in a variable, which is then saved as part of the

154 tasks context. */

155 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;

156

157 return pxTopOfStack;

158 }

159 /*-----------------------------------------------------------*/

160

161 BaseType_t xPortStartScheduler( void )

162 {

163 /* Start the timer that generates the tick ISR. Interrupts are disabled

164 here already. */

165 prvSetupTimerInterrupt();

166

167 /* Start the first task. */

168 vPortISRStartFirstTask();

169

170 /* Should not get here! */

171 return 0;

172 }

173 /*-----------------------------------------------------------*/

174

175 void vPortEndScheduler( void )

176 {

177 /* It is unlikely that the ARM port will require this function as there

178 is nothing to return to. */

179 }

180 /*-----------------------------------------------------------*/

181

182 /*

183 * Setup the timer 0 to generate the tick interrupts at the required frequency.

184 */

185 static void prvSetupTimerInterrupt( void )

186 {

187 AT91PS_PITC pxPIT = AT91C_BASE_PITC;

188

189 /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends

190 on whether the preemptive or cooperative scheduler is being used. */

191 #if configUSE_PREEMPTION == 0

192

193 extern void ( vNonPreemptiveTick ) ( void );

194 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );

195

196 #else

197

198 extern void ( vPreemptiveTick )( void );

199 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );

200

201 #endif

202

203 /* Configure the PIT period. */

204 pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;

205

206 /* Enable the interrupt. Global interrupts are disables at this point so

207 this is safe. */

208 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;

209 }

210 /*-----------------------------------------------------------*/

211

212

213