begriffs open source - freertos/blob - portable/GCC/ARM7

1 /*

2 * FreeRTOS SMP Kernel V202110.00

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a copy of

6 * this software and associated documentation files (the "Software"), to deal in

7 * the Software without restriction, including without limitation the rights to

8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of

9 * the Software, and to permit persons to whom the Software is furnished to do so,

10 * subject to the following conditions:

11 *

12 * The above copyright notice and this permission notice shall be included in all

13 * copies or substantial portions of the Software.

14 *

15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS

17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR

18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER

19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

21 *

22 * https://www.FreeRTOS.org

23 * https://github.com/FreeRTOS

24 *

25 * 1 tab == 4 spaces!

26 */

27

28

29 /*-----------------------------------------------------------

30 * Components that can be compiled to either ARM or THUMB mode are

31 * contained in port.c The ISR routines, which can only be compiled

32 * to ARM mode, are contained in this file.

33 *----------------------------------------------------------*/

34

35 /*

36 Changes from V2.5.2

37

38 + The critical section management functions have been changed. These no

39 longer modify the stack and are safe to use at all optimisation levels.

40 The functions are now also the same for both ARM and THUMB modes.

41

42 Changes from V2.6.0

43

44 + Removed the 'static' from the definition of vNonPreemptiveTick() to

45 allow the demo to link when using the cooperative scheduler.

46

47 Changes from V3.2.4

48

49 + The assembler statements are now included in a single asm block rather

50 than each line having its own asm block.

51 */

52

53

54 /* Scheduler includes. */

55 #include "FreeRTOS.h"

56

57 /* Constants required to handle interrupts. */

58 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )

59 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )

60

61 /* Constants required to handle critical sections. */

62 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )

63 volatile uint32_t ulCriticalNesting = 9999UL;

64

65 /*-----------------------------------------------------------*/

66

67 /* ISR to handle manual context switches (from a call to taskYIELD()). */

68 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));

69

70 /*

71 * The scheduler can only be started from ARM mode, hence the inclusion of this

72 * function here.

73 */

74 void vPortISRStartFirstTask( void );

75 /*-----------------------------------------------------------*/

76

77 void vPortISRStartFirstTask( void )

78 {

79 /* Simply start the scheduler. This is included here as it can only be

80 called from ARM mode. */

81 portRESTORE_CONTEXT();

82 }

83 /*-----------------------------------------------------------*/

84

85 /*

86 * Called by portYIELD() or taskYIELD() to manually force a context switch.

87 *

88 * When a context switch is performed from the task level the saved task

89 * context is made to look as if it occurred from within the tick ISR. This

90 * way the same restore context function can be used when restoring the context

91 * saved from the ISR or that saved from a call to vPortYieldProcessor.

92 */

93 void vPortYieldProcessor( void )

94 {

95 /* Within an IRQ ISR the link register has an offset from the true return

96 address, but an SWI ISR does not. Add the offset manually so the same

97 ISR return code can be used in both cases. */

98 __asm volatile ( "ADD LR, LR, #4" );

99

100 /* Perform the context switch. First save the context of the current task. */

101 portSAVE_CONTEXT();

102

103 /* Find the highest priority task that is ready to run. */

104 __asm volatile ( "bl vTaskSwitchContext" );

105

106 /* Restore the context of the new task. */

107 portRESTORE_CONTEXT();

108 }

109 /*-----------------------------------------------------------*/

110

111 /*

112 * The ISR used for the scheduler tick.

113 */

114 void vTickISR( void ) __attribute__((naked));

115 void vTickISR( void )

116 {

117 /* Save the context of the interrupted task. */

118 portSAVE_CONTEXT();

119

120 /* Increment the RTOS tick count, then look for the highest priority

121 task that is ready to run. */

122 __asm volatile

123 (

124 " bl xTaskIncrementTick \t\n" \

125 " cmp r0, #0 \t\n" \

126 " beq SkipContextSwitch \t\n" \

127 " bl vTaskSwitchContext \t\n" \

128 "SkipContextSwitch: \t\n"

129 );

130

131 /* Ready for the next interrupt. */

132 T0_IR = portTIMER_MATCH_ISR_BIT;

133 VICVectAddr = portCLEAR_VIC_INTERRUPT;

134

135 /* Restore the context of the new task. */

136 portRESTORE_CONTEXT();

137 }

138 /*-----------------------------------------------------------*/

139

140 /*

141 * The interrupt management utilities can only be called from ARM mode. When

142 * THUMB_INTERWORK is defined the utilities are defined as functions here to

143 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then

144 * the utilities are defined as macros in portmacro.h - as per other ports.

145 */

146 #ifdef THUMB_INTERWORK

147

148 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));

149 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));

150

151 void vPortDisableInterruptsFromThumb( void )

152 {

153 __asm volatile (

154 "STMDB SP!, {R0} \n\t" /* Push R0. */

155 "MRS R0, CPSR \n\t" /* Get CPSR. */

156 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */

157 "MSR CPSR, R0 \n\t" /* Write back modified value. */

158 "LDMIA SP!, {R0} \n\t" /* Pop R0. */

159 "BX R14" ); /* Return back to thumb. */

160 }

161

162 void vPortEnableInterruptsFromThumb( void )

163 {

164 __asm volatile (

165 "STMDB SP!, {R0} \n\t" /* Push R0. */

166 "MRS R0, CPSR \n\t" /* Get CPSR. */

167 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */

168 "MSR CPSR, R0 \n\t" /* Write back modified value. */

169 "LDMIA SP!, {R0} \n\t" /* Pop R0. */

170 "BX R14" ); /* Return back to thumb. */

171 }

172

173 #endif /* THUMB_INTERWORK */

174

175 /* The code generated by the GCC compiler uses the stack in different ways at

176 different optimisation levels. The interrupt flags can therefore not always

177 be saved to the stack. Instead the critical section nesting level is stored

178 in a variable, which is then saved as part of the stack context. */

179 void vPortEnterCritical( void )

180 {

181 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */

182 __asm volatile (

183 "STMDB SP!, {R0} \n\t" /* Push R0. */

184 "MRS R0, CPSR \n\t" /* Get CPSR. */

185 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */

186 "MSR CPSR, R0 \n\t" /* Write back modified value. */

187 "LDMIA SP!, {R0}" ); /* Pop R0. */

188

189 /* Now interrupts are disabled ulCriticalNesting can be accessed

190 directly. Increment ulCriticalNesting to keep a count of how many times

191 portENTER_CRITICAL() has been called. */

192 ulCriticalNesting++;

193 }

194

195 void vPortExitCritical( void )

196 {

197 if( ulCriticalNesting > portNO_CRITICAL_NESTING )

198 {

199 /* Decrement the nesting count as we are leaving a critical section. */

200 ulCriticalNesting--;

201

202 /* If the nesting level has reached zero then interrupts should be

203 re-enabled. */

204 if( ulCriticalNesting == portNO_CRITICAL_NESTING )

205 {

206 /* Enable interrupts as per portEXIT_CRITICAL(). */

207 __asm volatile (

208 "STMDB SP!, {R0} \n\t" /* Push R0. */

209 "MRS R0, CPSR \n\t" /* Get CPSR. */

210 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */

211 "MSR CPSR, R0 \n\t" /* Write back modified value. */

212 "LDMIA SP!, {R0}" ); /* Pop R0. */

213 }

214 }

215 }