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RISC-V port updates: The machine timer compare register can now be for any HART...
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2019-09-04 Richard BarryRISC-V port updates: The machine timer compare registe...
2019-09-04 Richard BarryMinor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_S...
2019-09-03 Richard BarryAdd IAR RISC-V port to SVN - a work in progress.
2019-08-27 Richard BarryCorrect alignment of stack top in RISC-V port when...
2019-08-25 Richard Barry+ Moved the History.txt file from the website git repo...
2019-08-04 Richard BarryTidy up Win32 port layer - include addition of new...
2019-07-24 Richard BarryContinued to work on the MQTT demo project.
2019-07-12 Richard BarryOnly partially implemented and may get reverted -...
2019-07-04 Richard BarryAdd vPortGetHeapStats() function to query heap statistics.
2019-05-13 Richard BarryAdded additional xMessageBufferSpacesAvailable() (plura...
2019-05-11 Richard BarryUpdate version number ready for next release.
2019-05-09 Gaurav AggarwalDelete the not needed file missed in last commit
2019-05-09 Gaurav AggarwalDo not strip required symbols when LTO is on
2019-05-02 Gaurav AggarwalAdd Cortex M23 GCC and IAR ports. Add demo projects...
2019-04-29 Richard BarryBasic 64-bit RISC-V port now functional. RISC-V port...
2019-04-25 Richard BarryAdded portMEMORY_BARRIER() implemented as __asm volatil...
2019-04-21 Richard BarryAdded portMEMORY_BARRIER() implemented as __asm volatil...
2019-04-17 Richard BarryFix potential memory leak in the Win32 FreeRTOS+TCP...
2019-03-28 Gaurav AggarwalExport port architecture name for COrtex-M33. This...
2019-03-18 Gaurav AggarwalFix spelling of priority in comments.
2019-03-08 Richard BarryCorrecting spelling mistakes in comments only.
2019-03-08 Richard BarryPrepare the RISC-V port layer for addition of 64-bit...
2019-02-21 Gaurav AggarwalChange type of usStackDepth to configSTACK_DEPTH_TYPE.
2019-02-20 Gaurav AggarwalFix Build and Links failure in MPU projects. Minor...
2019-02-20 Richard BarryAdd instructions on building the Cortex-M33 secure...
2019-02-20 Gaurav AggarwalAdd support for running FreeRTOS on Secure Side only...
2019-02-19 Richard BarryUpdate the common demo death.c to use the updated macro...
2019-02-19 Gaurav AggarwalFirst Official Release of ARMV8M Support. This release...
2019-02-17 Richard BarryUpdate version number in readiness for V10.2.0 release.
2019-02-17 Gaurav AggarwalSync the Renesas port to AFR Git Repo
2019-02-16 Richard BarryReplace the pdf RISC-V documentation with links to...
2019-02-16 Richard BarryFix bug in core_cm3.c atomic macros.
2019-02-08 Richard BarryEnsure eTaskGetState() is brought in automatically...
2019-01-21 Richard BarryAdd xTaskGetIdleRunTimeCounter() API function to return...
2019-01-16 Gaurav AggarwalCopyright updates from Cadence.
2018-12-31 Richard BarryMove the 'generic' version of freertos_risc_v_chip_spec...
2018-12-30 Richard BarryRe-org of RISC-V file structure and naming step 2.
2018-12-30 Richard BarryRe-org of RISC-V file structure and naming step 1.
2018-12-30 Richard BarryUpdate RSIC-V port layer after testing saving and recei...
2018-12-30 Richard BarryMove the RISC-V pxPortInitialiseStack() implementation...
2018-12-28 Richard BarryAllow the size of the stack used by many of the standar...
2018-12-24 Richard BarryRename directories in the RISC-V port.
2018-12-17 Richard BarryRemove "FromISR' functions from the list of functions...
2018-12-16 Richard BarryRework RISC-V portASM.S to make it easier to add in...
2018-12-16 Richard BarrySave changes to the RISC-V port layer before making...
2018-12-04 Richard BarryUpdate RISC-V port to use a separate interrupt stack.
2018-11-28 Richard BarrySome efficiency improvements in Risc-V port.
2018-11-24 Richard BarryFirst task running in RISC-V-Qemu-sifive_e-FreedomStudi...
2018-11-20 Richard BarryProvide each Risc V task with an initial mstatus regist...
2018-11-19 Richard BarryUpdate Risc-V port to use environment call in place...
2018-11-06 Richard BarryContinue work on Risc V port.
2018-10-08 Richard BarryAdd xTaskGetApplicationTaskTagFromISR(), which is an...
2018-09-30 Richard BarryAdded uxTaskGetStackHighWaterMark2(), which is the...
2018-09-27 Richard BarryRISC-V tasks now context switching to each other using...
2018-09-23 Richard BarryAdd trap handler to RISC-V port so there is no dependen...
2018-09-12 Richard BarryRISC-V:
2018-09-10 Richard BarryRISC-V work in progress:
2018-09-07 Richard BarryUpdate version numbers ready for release.
2018-08-29 Richard BarryCase unused return values for memset and memcpy to...
2018-08-22 Richard BarryUpdate copyright date ready for tagging V10.1.0.
2018-08-21 Richard BarryUpdate version numbers in preparation for a new release.
2018-08-21 Richard BarryUpdate demo project for Tensilita - work in progres..
2018-08-07 Gaurav AggarwalMerge bug fixes from Cadence
2018-07-07 Richard BarryUpdate RISC-V project to used official port stubs in...
2018-07-07 Richard BarryAdd stubs for official RISC-V RV32 port.
2018-06-20 Richard BarrySmall change to the directory name in which the RISC...
2018-06-20 Richard BarryAdd RISCV port layer.
2018-06-14 Gaurav AggarwalAdd Xtensa port
2018-06-11 Richard BarryFix misra violations in queue.c by introducing a union...
2018-06-03 Richard BarryFirst pass at updating from MISRA 2004 to MISRA 2012:
2018-05-17 Richard BarryMinor updates to comments only.
2018-03-14 Richard BarryImport the code coverage test additions from the (unpub...
2018-03-04 Richard BarryIntroduce xMessageBufferNextLengthBytes() and tests...
2018-01-30 Richard BarryMicroblaze port: Place critical section around XIntc_E...
2017-12-18 Richard BarryRoll up the minor changes checked into svn since V10...
2017-11-29 Richard BarryUpdate to MIT licensed FreeRTOS V10.0.0 - see https...
2017-08-09 Richard BarryUpdate TriCore port to work with latest GCC compiler.
2017-05-30 Richard BarryCorrect long time mis-spelled portINITIAL_EXEC_RETURN...
2017-04-10 Richard BarryAdd more "memory" clobbers into the MPU ports to make...
2017-04-10 Richard BarryAdd more "memory" clobbers into asm code of GCC/ARM_CRx...
2017-04-10 Richard BarryUpdates to prevent warnings when compiled with LLVM.
2017-04-09 Richard BarryEnsure the PIC32 interrupt stack is 8 byte aligned...
2017-03-28 Richard BarryUpdates to the Cortex-M tickless idle code to reduce...
2017-03-08 Richard BarryHousekeeping check-in, no code changes.
2017-03-07 Richard BarryAdd additional memory barriers into ARM GCC asm code...
2017-02-24 Richard BarryIntroduce vTaskInternalSetTimeOutState() which does...
2017-01-22 Richard BarryUpdate version number in preparation for maintenance...
2017-01-19 Richard BarryUpdate BSP source files for UltraScale Cortex-A53 and...
2017-01-18 Richard BarryCorrect alignment issue in GCC and RVDS Cortex-A9 port...
2017-01-04 Richard BarryIncrease the priority of the Windows threads used by...
2016-11-25 Richard BarryUpdate TaskNotify.c to test the condition where a direc...
2016-09-20 Richard BarryAdd support for statically allocated memory protected...
2016-08-16 Richard BarryChanges to core code and port layer:
2016-06-28 Richard BarryRemove clrex instruction from Cortex-M ports again...
2016-06-27 Richard BarryImprovements to the Cortex-M ports:
2016-05-20 Richard BarryPrepare for V9.0.0 release:
2016-05-19 Richard BarryPrepare for V9.0.0 release.
2016-05-18 Richard BarryIncrease the test coverage of the GCC MPU demo that...
2016-05-18 Richard BarryAdd GCC ARM Cortex-M4F MPU port.
2016-05-10 Richard BarryRecreated MicroBlaze example using Vivado 2016.1 -...
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